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Searched refs:AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h1844 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
1852 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h1844 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
1852 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h1929 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
1937 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h1933 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
1941 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h1932 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
1940 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2700 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
2703 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2700 #define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U) macro
2703 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)