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Searched refs:AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h1807 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
1815 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h1807 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
1815 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h1892 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
1900 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h1896 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
1904 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h1895 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
1903 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2678 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
2681 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2678 #define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U) macro
2681 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)