Home
last modified time | relevance | path

Searched refs:AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h1777 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
1785 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h1777 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
1785 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h1862 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
1870 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h1866 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
1874 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h1865 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
1873 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2663 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
2666 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2663 #define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U) macro
2666 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)