Home
last modified time | relevance | path

Searched refs:AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h1536 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
1544 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h1536 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
1544 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h1621 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
1629 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h1625 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
1633 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h1624 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
1632 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2532 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
2535 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2532 #define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U) macro
2535 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)