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Searched refs:AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h1409 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
1417 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h1409 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
1417 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h1494 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
1502 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h1498 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
1506 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h1497 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
1505 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2465 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
2468 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2465 #define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U) macro
2468 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)