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Searched refs:AHBSC_RAMG_MEM_RULE_RULE4_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h2775 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2783 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
DMCXN546_cm33_core1.h2775 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2783 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h2775 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2783 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
DMCXN547_cm33_core1.h2775 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2783 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h2809 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2817 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
DMCXN947_cm33_core0.h2809 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2817 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h2809 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2817 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)
DMCXN946_cm33_core1.h2809 #define AHBSC_RAMG_MEM_RULE_RULE4_MASK (0x30000U) macro
2817 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE4_MASK)