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Searched refs:ADMA__LPCG_UART1_IPG_CLK_BASE (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.h271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h79583 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
79585 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
79587 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h79583 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
79585 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
79587 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h79583 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
79585 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
79587 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h79583 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
79585 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
79587 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h109392 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109394 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109396 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h109392 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109394 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109396 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h109392 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109394 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109396 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h113064 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
113066 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
113068 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
DMIMX8QX6_cm4.h109394 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109396 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109398 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h109394 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109396 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109398 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h109393 #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) macro
109395 …ne ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE)
109397 #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE }

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