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Searched refs:ADC_GC_ACREN_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/imx/drivers/
Dadc_imx6sx.c389 ADC_GC_REG(base) &= ~(ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); in ADC_SetCmpMode()
395 ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACFGT_MASK) & (~ADC_GC_ACREN_MASK); in ADC_SetCmpMode()
401 ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); in ADC_SetCmpMode()
411 ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); in ADC_SetCmpMode()
421 ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; in ADC_SetCmpMode()
431 ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; in ADC_SetCmpMode()
/hal_nxp-latest/mcux/mcux-sdk/drivers/adc_12b1msps_sar/
Dfsl_adc.c315 tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); in ADC_SetHardwareCompareConfig()
333 tmp32 |= ADC_GC_ACREN_MASK; in ADC_SetHardwareCompareConfig()
336 tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK; in ADC_SetHardwareCompareConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h789 #define ADC_GC_ACREN_MASK (0x4U) macro
795 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h1143 #define ADC_GC_ACREN_MASK (0x4U) macro
1149 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h1286 #define ADC_GC_ACREN_MASK (0x4U) macro
1292 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h1306 #define ADC_GC_ACREN_MASK (0x4U) macro
1312 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h1517 #define ADC_GC_ACREN_MASK (0x4U) macro
1523 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h1496 #define ADC_GC_ACREN_MASK (0x4U) macro
1502 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h1520 #define ADC_GC_ACREN_MASK (0x4U) macro
1526 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h1498 #define ADC_GC_ACREN_MASK (0x4U) macro
1504 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h1573 #define ADC_GC_ACREN_MASK (0x4U) macro
1579 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h1655 #define ADC_GC_ACREN_MASK (0x4U) macro
1661 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h1577 #define ADC_GC_ACREN_MASK (0x4U) macro
1583 … (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h412 #define ADC_GC_ACREN_MASK 0x4u macro