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Searched refs:ADC_CLP1_CLP1_MASK (Results 1 – 25 of 79) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K144W_ADC.h375 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
378 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K116_ADC.h371 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
374 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K118_ADC.h371 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
374 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K142W_ADC.h375 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
378 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K142_ADC.h375 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
378 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K144_ADC.h375 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
378 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K146_ADC.h840 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
843 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
DS32K148_ADC.h860 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
863 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/adc12/
Dfsl_adc12.c105 uint32_t CLP1 = ((base->CLP1 & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT); in ADC12_GetCalibrationStatus()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h550 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
552 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h667 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
669 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/
DMCXC141.h721 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
724 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/
DMCXC142.h719 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
722 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h525 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
527 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/
DMCXC242.h721 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
724 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h676 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
678 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h692 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
695 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h692 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
695 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h735 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
737 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h690 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
693 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/
DMCXC244.h692 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
695 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h735 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
737 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h649 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
651 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h621 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
625 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h748 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
750 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)

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