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Searched refs:ADC_CFG_ADTRG_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/adc_12b1msps_sar/
Dfsl_adc.h359 base->CFG |= ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
363 base->CFG &= ~ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
Dfsl_adc.c75 tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ in ADC_Init()
232 if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) in ADC_DoAutoCalibration()
/hal_nxp-latest/imx/drivers/
Dadc_imx6sx.c112 ADC_CFG_REG(base) |= ADC_CFG_ADTRG_MASK; in ADC_SetConvertTrigMode()
114 ADC_CFG_REG(base) &= ~ADC_CFG_ADTRG_MASK; in ADC_SetConvertTrigMode()
Dadc_imx6sx.h200 return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADTRG_MASK) >> ADC_CFG_ADTRG_SHIFT); in ADC_GetConvertTrigMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h743 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
749 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h1097 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1103 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h1240 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1246 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h1260 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1266 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h1471 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1477 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h1450 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1456 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h1474 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1480 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h1452 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1458 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h1527 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1533 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h1609 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1615 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h1531 #define ADC_CFG_ADTRG_MASK (0x2000U) macro
1537 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h400 #define ADC_CFG_ADTRG_MASK 0x2000u macro