1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_ADC.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_ADC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_ADC_H_) /* Check if memory map has not been already included */ 58 #define S32K148_ADC_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ADC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ADC - Size of Registers Arrays */ 72 #define ADC_CV_COUNT 2u 73 #define ADC_SC1ZZ_COUNT 16u 74 #define ADC_RZZ_COUNT 16u 75 76 /** ADC - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t SC1A; /**< ADC Status and Control Register 1, offset: 0x0 */ 79 __IO uint32_t SC1B; /**< ADC Status and Control Register 1, offset: 0x4 */ 80 __IO uint32_t SC1C; /**< ADC Status and Control Register 1, offset: 0x8 */ 81 __IO uint32_t SC1D; /**< ADC Status and Control Register 1, offset: 0xC */ 82 __IO uint32_t SC1E; /**< ADC Status and Control Register 1, offset: 0x10 */ 83 __IO uint32_t SC1F; /**< ADC Status and Control Register 1, offset: 0x14 */ 84 __IO uint32_t SC1G; /**< ADC Status and Control Register 1, offset: 0x18 */ 85 __IO uint32_t SC1H; /**< ADC Status and Control Register 1, offset: 0x1C */ 86 __IO uint32_t SC1I; /**< ADC Status and Control Register 1, offset: 0x20 */ 87 __IO uint32_t SC1J; /**< ADC Status and Control Register 1, offset: 0x24 */ 88 __IO uint32_t SC1K; /**< ADC Status and Control Register 1, offset: 0x28 */ 89 __IO uint32_t SC1L; /**< ADC Status and Control Register 1, offset: 0x2C */ 90 __IO uint32_t SC1M; /**< ADC Status and Control Register 1, offset: 0x30 */ 91 __IO uint32_t SC1N; /**< ADC Status and Control Register 1, offset: 0x34 */ 92 __IO uint32_t SC1O; /**< ADC Status and Control Register 1, offset: 0x38 */ 93 __IO uint32_t SC1P; /**< ADC Status and Control Register 1, offset: 0x3C */ 94 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ 95 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ 96 __I uint32_t RA; /**< ADC Data Result Registers, offset: 0x48 */ 97 __I uint32_t RB; /**< ADC Data Result Registers, offset: 0x4C */ 98 __I uint32_t RC; /**< ADC Data Result Registers, offset: 0x50 */ 99 __I uint32_t RD; /**< ADC Data Result Registers, offset: 0x54 */ 100 __I uint32_t RE; /**< ADC Data Result Registers, offset: 0x58 */ 101 __I uint32_t RF; /**< ADC Data Result Registers, offset: 0x5C */ 102 __I uint32_t RG; /**< ADC Data Result Registers, offset: 0x60 */ 103 __I uint32_t RH; /**< ADC Data Result Registers, offset: 0x64 */ 104 __I uint32_t RI; /**< ADC Data Result Registers, offset: 0x68 */ 105 __I uint32_t RJ; /**< ADC Data Result Registers, offset: 0x6C */ 106 __I uint32_t RK; /**< ADC Data Result Registers, offset: 0x70 */ 107 __I uint32_t RL; /**< ADC Data Result Registers, offset: 0x74 */ 108 __I uint32_t RM; /**< ADC Data Result Registers, offset: 0x78 */ 109 __I uint32_t RN; /**< ADC Data Result Registers, offset: 0x7C */ 110 __I uint32_t RO; /**< ADC Data Result Registers, offset: 0x80 */ 111 __I uint32_t RP; /**< ADC Data Result Registers, offset: 0x84 */ 112 __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ 113 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ 114 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ 115 __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ 116 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ 117 __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ 118 __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ 119 __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ 120 __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ 121 __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ 122 __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ 123 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ 124 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ 125 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ 126 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ 127 __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ 128 __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ 129 __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ 130 __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ 131 __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ 132 __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ 133 __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ 134 __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ 135 __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ 136 uint8_t RESERVED_0[28]; 137 __IO uint32_t ASC1A; /**< ADC Status and Control Register 1, offset: 0x108 */ 138 __IO uint32_t ASC1B; /**< ADC Status and Control Register 1, offset: 0x10C */ 139 __IO uint32_t ASC1C; /**< ADC Status and Control Register 1, offset: 0x110 */ 140 __IO uint32_t ASC1D; /**< ADC Status and Control Register 1, offset: 0x114 */ 141 __IO uint32_t ASC1E; /**< ADC Status and Control Register 1, offset: 0x118 */ 142 __IO uint32_t ASC1F; /**< ADC Status and Control Register 1, offset: 0x11C */ 143 __IO uint32_t ASC1G; /**< ADC Status and Control Register 1, offset: 0x120 */ 144 __IO uint32_t ASC1H; /**< ADC Status and Control Register 1, offset: 0x124 */ 145 __IO uint32_t ASC1I; /**< ADC Status and Control Register 1, offset: 0x128 */ 146 __IO uint32_t ASC1J; /**< ADC Status and Control Register 1, offset: 0x12C */ 147 __IO uint32_t ASC1K; /**< ADC Status and Control Register 1, offset: 0x130 */ 148 __IO uint32_t ASC1L; /**< ADC Status and Control Register 1, offset: 0x134 */ 149 __IO uint32_t ASC1M; /**< ADC Status and Control Register 1, offset: 0x138 */ 150 __IO uint32_t ASC1N; /**< ADC Status and Control Register 1, offset: 0x13C */ 151 __IO uint32_t ASC1O; /**< ADC Status and Control Register 1, offset: 0x140 */ 152 __IO uint32_t ASC1P; /**< ADC Status and Control Register 1, offset: 0x144 */ 153 __IO uint32_t SC1[ADC_SC1ZZ_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x148, array step: 0x4 */ 154 __I uint32_t ARA; /**< ADC Data Result Registers, offset: 0x188 */ 155 __I uint32_t ARB; /**< ADC Data Result Registers, offset: 0x18C */ 156 __I uint32_t ARC; /**< ADC Data Result Registers, offset: 0x190 */ 157 __I uint32_t ARD; /**< ADC Data Result Registers, offset: 0x194 */ 158 __I uint32_t ARE; /**< ADC Data Result Registers, offset: 0x198 */ 159 __I uint32_t ARF; /**< ADC Data Result Registers, offset: 0x19C */ 160 __I uint32_t ARG; /**< ADC Data Result Registers, offset: 0x1A0 */ 161 __I uint32_t ARH; /**< ADC Data Result Registers, offset: 0x1A4 */ 162 __I uint32_t ARI; /**< ADC Data Result Registers, offset: 0x1A8 */ 163 __I uint32_t ARJ; /**< ADC Data Result Registers, offset: 0x1AC */ 164 __I uint32_t ARK; /**< ADC Data Result Registers, offset: 0x1B0 */ 165 __I uint32_t ARL; /**< ADC Data Result Registers, offset: 0x1B4 */ 166 __I uint32_t ARM; /**< ADC Data Result Registers, offset: 0x1B8 */ 167 __I uint32_t ARN; /**< ADC Data Result Registers, offset: 0x1BC */ 168 __I uint32_t ARO; /**< ADC Data Result Registers, offset: 0x1C0 */ 169 __I uint32_t ARP; /**< ADC Data Result Registers, offset: 0x1C4 */ 170 __I uint32_t R[ADC_RZZ_COUNT]; /**< ADC Data Result Registers, array offset: 0x1C8, array step: 0x4 */ 171 } ADC_Type, *ADC_MemMapPtr; 172 173 /** Number of instances of the ADC module. */ 174 #define ADC_INSTANCE_COUNT (2u) 175 176 /* ADC - Peripheral instance base addresses */ 177 /** Peripheral ADC0 base address */ 178 #define IP_ADC0_BASE (0x4003B000u) 179 /** Peripheral ADC0 base pointer */ 180 #define IP_ADC0 ((ADC_Type *)IP_ADC0_BASE) 181 /** Peripheral ADC1 base address */ 182 #define IP_ADC1_BASE (0x40027000u) 183 /** Peripheral ADC1 base pointer */ 184 #define IP_ADC1 ((ADC_Type *)IP_ADC1_BASE) 185 /** Array initializer of ADC peripheral base addresses */ 186 #define IP_ADC_BASE_ADDRS { IP_ADC0_BASE, IP_ADC1_BASE } 187 /** Array initializer of ADC peripheral base pointers */ 188 #define IP_ADC_BASE_PTRS { IP_ADC0, IP_ADC1 } 189 190 /* ---------------------------------------------------------------------------- 191 -- ADC Register Masks 192 ---------------------------------------------------------------------------- */ 193 194 /*! 195 * @addtogroup ADC_Register_Masks ADC Register Masks 196 * @{ 197 */ 198 199 /*! @name SC1A - ADC Status and Control Register 1 */ 200 /*! @{ */ 201 202 #define ADC_SC1A_ADCH_MASK (0x3FU) 203 #define ADC_SC1A_ADCH_SHIFT (0U) 204 #define ADC_SC1A_ADCH_WIDTH (6U) 205 #define ADC_SC1A_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_ADCH_SHIFT)) & ADC_SC1A_ADCH_MASK) 206 207 #define ADC_SC1A_AIEN_MASK (0x40U) 208 #define ADC_SC1A_AIEN_SHIFT (6U) 209 #define ADC_SC1A_AIEN_WIDTH (1U) 210 #define ADC_SC1A_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_AIEN_SHIFT)) & ADC_SC1A_AIEN_MASK) 211 212 #define ADC_SC1A_COCO_MASK (0x80U) 213 #define ADC_SC1A_COCO_SHIFT (7U) 214 #define ADC_SC1A_COCO_WIDTH (1U) 215 #define ADC_SC1A_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1A_COCO_SHIFT)) & ADC_SC1A_COCO_MASK) 216 /*! @} */ 217 218 /*! @name SC1B - ADC Status and Control Register 1 */ 219 /*! @{ */ 220 221 #define ADC_SC1B_ADCH_MASK (0x3FU) 222 #define ADC_SC1B_ADCH_SHIFT (0U) 223 #define ADC_SC1B_ADCH_WIDTH (6U) 224 #define ADC_SC1B_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_ADCH_SHIFT)) & ADC_SC1B_ADCH_MASK) 225 226 #define ADC_SC1B_AIEN_MASK (0x40U) 227 #define ADC_SC1B_AIEN_SHIFT (6U) 228 #define ADC_SC1B_AIEN_WIDTH (1U) 229 #define ADC_SC1B_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_AIEN_SHIFT)) & ADC_SC1B_AIEN_MASK) 230 231 #define ADC_SC1B_COCO_MASK (0x80U) 232 #define ADC_SC1B_COCO_SHIFT (7U) 233 #define ADC_SC1B_COCO_WIDTH (1U) 234 #define ADC_SC1B_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1B_COCO_SHIFT)) & ADC_SC1B_COCO_MASK) 235 /*! @} */ 236 237 /*! @name SC1C - ADC Status and Control Register 1 */ 238 /*! @{ */ 239 240 #define ADC_SC1C_ADCH_MASK (0x3FU) 241 #define ADC_SC1C_ADCH_SHIFT (0U) 242 #define ADC_SC1C_ADCH_WIDTH (6U) 243 #define ADC_SC1C_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_ADCH_SHIFT)) & ADC_SC1C_ADCH_MASK) 244 245 #define ADC_SC1C_AIEN_MASK (0x40U) 246 #define ADC_SC1C_AIEN_SHIFT (6U) 247 #define ADC_SC1C_AIEN_WIDTH (1U) 248 #define ADC_SC1C_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_AIEN_SHIFT)) & ADC_SC1C_AIEN_MASK) 249 250 #define ADC_SC1C_COCO_MASK (0x80U) 251 #define ADC_SC1C_COCO_SHIFT (7U) 252 #define ADC_SC1C_COCO_WIDTH (1U) 253 #define ADC_SC1C_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1C_COCO_SHIFT)) & ADC_SC1C_COCO_MASK) 254 /*! @} */ 255 256 /*! @name SC1D - ADC Status and Control Register 1 */ 257 /*! @{ */ 258 259 #define ADC_SC1D_ADCH_MASK (0x3FU) 260 #define ADC_SC1D_ADCH_SHIFT (0U) 261 #define ADC_SC1D_ADCH_WIDTH (6U) 262 #define ADC_SC1D_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_ADCH_SHIFT)) & ADC_SC1D_ADCH_MASK) 263 264 #define ADC_SC1D_AIEN_MASK (0x40U) 265 #define ADC_SC1D_AIEN_SHIFT (6U) 266 #define ADC_SC1D_AIEN_WIDTH (1U) 267 #define ADC_SC1D_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_AIEN_SHIFT)) & ADC_SC1D_AIEN_MASK) 268 269 #define ADC_SC1D_COCO_MASK (0x80U) 270 #define ADC_SC1D_COCO_SHIFT (7U) 271 #define ADC_SC1D_COCO_WIDTH (1U) 272 #define ADC_SC1D_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1D_COCO_SHIFT)) & ADC_SC1D_COCO_MASK) 273 /*! @} */ 274 275 /*! @name SC1E - ADC Status and Control Register 1 */ 276 /*! @{ */ 277 278 #define ADC_SC1E_ADCH_MASK (0x3FU) 279 #define ADC_SC1E_ADCH_SHIFT (0U) 280 #define ADC_SC1E_ADCH_WIDTH (6U) 281 #define ADC_SC1E_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_ADCH_SHIFT)) & ADC_SC1E_ADCH_MASK) 282 283 #define ADC_SC1E_AIEN_MASK (0x40U) 284 #define ADC_SC1E_AIEN_SHIFT (6U) 285 #define ADC_SC1E_AIEN_WIDTH (1U) 286 #define ADC_SC1E_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_AIEN_SHIFT)) & ADC_SC1E_AIEN_MASK) 287 288 #define ADC_SC1E_COCO_MASK (0x80U) 289 #define ADC_SC1E_COCO_SHIFT (7U) 290 #define ADC_SC1E_COCO_WIDTH (1U) 291 #define ADC_SC1E_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1E_COCO_SHIFT)) & ADC_SC1E_COCO_MASK) 292 /*! @} */ 293 294 /*! @name SC1F - ADC Status and Control Register 1 */ 295 /*! @{ */ 296 297 #define ADC_SC1F_ADCH_MASK (0x3FU) 298 #define ADC_SC1F_ADCH_SHIFT (0U) 299 #define ADC_SC1F_ADCH_WIDTH (6U) 300 #define ADC_SC1F_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_ADCH_SHIFT)) & ADC_SC1F_ADCH_MASK) 301 302 #define ADC_SC1F_AIEN_MASK (0x40U) 303 #define ADC_SC1F_AIEN_SHIFT (6U) 304 #define ADC_SC1F_AIEN_WIDTH (1U) 305 #define ADC_SC1F_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_AIEN_SHIFT)) & ADC_SC1F_AIEN_MASK) 306 307 #define ADC_SC1F_COCO_MASK (0x80U) 308 #define ADC_SC1F_COCO_SHIFT (7U) 309 #define ADC_SC1F_COCO_WIDTH (1U) 310 #define ADC_SC1F_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1F_COCO_SHIFT)) & ADC_SC1F_COCO_MASK) 311 /*! @} */ 312 313 /*! @name SC1G - ADC Status and Control Register 1 */ 314 /*! @{ */ 315 316 #define ADC_SC1G_ADCH_MASK (0x3FU) 317 #define ADC_SC1G_ADCH_SHIFT (0U) 318 #define ADC_SC1G_ADCH_WIDTH (6U) 319 #define ADC_SC1G_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_ADCH_SHIFT)) & ADC_SC1G_ADCH_MASK) 320 321 #define ADC_SC1G_AIEN_MASK (0x40U) 322 #define ADC_SC1G_AIEN_SHIFT (6U) 323 #define ADC_SC1G_AIEN_WIDTH (1U) 324 #define ADC_SC1G_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_AIEN_SHIFT)) & ADC_SC1G_AIEN_MASK) 325 326 #define ADC_SC1G_COCO_MASK (0x80U) 327 #define ADC_SC1G_COCO_SHIFT (7U) 328 #define ADC_SC1G_COCO_WIDTH (1U) 329 #define ADC_SC1G_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1G_COCO_SHIFT)) & ADC_SC1G_COCO_MASK) 330 /*! @} */ 331 332 /*! @name SC1H - ADC Status and Control Register 1 */ 333 /*! @{ */ 334 335 #define ADC_SC1H_ADCH_MASK (0x3FU) 336 #define ADC_SC1H_ADCH_SHIFT (0U) 337 #define ADC_SC1H_ADCH_WIDTH (6U) 338 #define ADC_SC1H_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_ADCH_SHIFT)) & ADC_SC1H_ADCH_MASK) 339 340 #define ADC_SC1H_AIEN_MASK (0x40U) 341 #define ADC_SC1H_AIEN_SHIFT (6U) 342 #define ADC_SC1H_AIEN_WIDTH (1U) 343 #define ADC_SC1H_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_AIEN_SHIFT)) & ADC_SC1H_AIEN_MASK) 344 345 #define ADC_SC1H_COCO_MASK (0x80U) 346 #define ADC_SC1H_COCO_SHIFT (7U) 347 #define ADC_SC1H_COCO_WIDTH (1U) 348 #define ADC_SC1H_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1H_COCO_SHIFT)) & ADC_SC1H_COCO_MASK) 349 /*! @} */ 350 351 /*! @name SC1I - ADC Status and Control Register 1 */ 352 /*! @{ */ 353 354 #define ADC_SC1I_ADCH_MASK (0x3FU) 355 #define ADC_SC1I_ADCH_SHIFT (0U) 356 #define ADC_SC1I_ADCH_WIDTH (6U) 357 #define ADC_SC1I_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_ADCH_SHIFT)) & ADC_SC1I_ADCH_MASK) 358 359 #define ADC_SC1I_AIEN_MASK (0x40U) 360 #define ADC_SC1I_AIEN_SHIFT (6U) 361 #define ADC_SC1I_AIEN_WIDTH (1U) 362 #define ADC_SC1I_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_AIEN_SHIFT)) & ADC_SC1I_AIEN_MASK) 363 364 #define ADC_SC1I_COCO_MASK (0x80U) 365 #define ADC_SC1I_COCO_SHIFT (7U) 366 #define ADC_SC1I_COCO_WIDTH (1U) 367 #define ADC_SC1I_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1I_COCO_SHIFT)) & ADC_SC1I_COCO_MASK) 368 /*! @} */ 369 370 /*! @name SC1J - ADC Status and Control Register 1 */ 371 /*! @{ */ 372 373 #define ADC_SC1J_ADCH_MASK (0x3FU) 374 #define ADC_SC1J_ADCH_SHIFT (0U) 375 #define ADC_SC1J_ADCH_WIDTH (6U) 376 #define ADC_SC1J_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_ADCH_SHIFT)) & ADC_SC1J_ADCH_MASK) 377 378 #define ADC_SC1J_AIEN_MASK (0x40U) 379 #define ADC_SC1J_AIEN_SHIFT (6U) 380 #define ADC_SC1J_AIEN_WIDTH (1U) 381 #define ADC_SC1J_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_AIEN_SHIFT)) & ADC_SC1J_AIEN_MASK) 382 383 #define ADC_SC1J_COCO_MASK (0x80U) 384 #define ADC_SC1J_COCO_SHIFT (7U) 385 #define ADC_SC1J_COCO_WIDTH (1U) 386 #define ADC_SC1J_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1J_COCO_SHIFT)) & ADC_SC1J_COCO_MASK) 387 /*! @} */ 388 389 /*! @name SC1K - ADC Status and Control Register 1 */ 390 /*! @{ */ 391 392 #define ADC_SC1K_ADCH_MASK (0x3FU) 393 #define ADC_SC1K_ADCH_SHIFT (0U) 394 #define ADC_SC1K_ADCH_WIDTH (6U) 395 #define ADC_SC1K_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_ADCH_SHIFT)) & ADC_SC1K_ADCH_MASK) 396 397 #define ADC_SC1K_AIEN_MASK (0x40U) 398 #define ADC_SC1K_AIEN_SHIFT (6U) 399 #define ADC_SC1K_AIEN_WIDTH (1U) 400 #define ADC_SC1K_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_AIEN_SHIFT)) & ADC_SC1K_AIEN_MASK) 401 402 #define ADC_SC1K_COCO_MASK (0x80U) 403 #define ADC_SC1K_COCO_SHIFT (7U) 404 #define ADC_SC1K_COCO_WIDTH (1U) 405 #define ADC_SC1K_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1K_COCO_SHIFT)) & ADC_SC1K_COCO_MASK) 406 /*! @} */ 407 408 /*! @name SC1L - ADC Status and Control Register 1 */ 409 /*! @{ */ 410 411 #define ADC_SC1L_ADCH_MASK (0x3FU) 412 #define ADC_SC1L_ADCH_SHIFT (0U) 413 #define ADC_SC1L_ADCH_WIDTH (6U) 414 #define ADC_SC1L_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_ADCH_SHIFT)) & ADC_SC1L_ADCH_MASK) 415 416 #define ADC_SC1L_AIEN_MASK (0x40U) 417 #define ADC_SC1L_AIEN_SHIFT (6U) 418 #define ADC_SC1L_AIEN_WIDTH (1U) 419 #define ADC_SC1L_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_AIEN_SHIFT)) & ADC_SC1L_AIEN_MASK) 420 421 #define ADC_SC1L_COCO_MASK (0x80U) 422 #define ADC_SC1L_COCO_SHIFT (7U) 423 #define ADC_SC1L_COCO_WIDTH (1U) 424 #define ADC_SC1L_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1L_COCO_SHIFT)) & ADC_SC1L_COCO_MASK) 425 /*! @} */ 426 427 /*! @name SC1M - ADC Status and Control Register 1 */ 428 /*! @{ */ 429 430 #define ADC_SC1M_ADCH_MASK (0x3FU) 431 #define ADC_SC1M_ADCH_SHIFT (0U) 432 #define ADC_SC1M_ADCH_WIDTH (6U) 433 #define ADC_SC1M_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_ADCH_SHIFT)) & ADC_SC1M_ADCH_MASK) 434 435 #define ADC_SC1M_AIEN_MASK (0x40U) 436 #define ADC_SC1M_AIEN_SHIFT (6U) 437 #define ADC_SC1M_AIEN_WIDTH (1U) 438 #define ADC_SC1M_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_AIEN_SHIFT)) & ADC_SC1M_AIEN_MASK) 439 440 #define ADC_SC1M_COCO_MASK (0x80U) 441 #define ADC_SC1M_COCO_SHIFT (7U) 442 #define ADC_SC1M_COCO_WIDTH (1U) 443 #define ADC_SC1M_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1M_COCO_SHIFT)) & ADC_SC1M_COCO_MASK) 444 /*! @} */ 445 446 /*! @name SC1N - ADC Status and Control Register 1 */ 447 /*! @{ */ 448 449 #define ADC_SC1N_ADCH_MASK (0x3FU) 450 #define ADC_SC1N_ADCH_SHIFT (0U) 451 #define ADC_SC1N_ADCH_WIDTH (6U) 452 #define ADC_SC1N_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_ADCH_SHIFT)) & ADC_SC1N_ADCH_MASK) 453 454 #define ADC_SC1N_AIEN_MASK (0x40U) 455 #define ADC_SC1N_AIEN_SHIFT (6U) 456 #define ADC_SC1N_AIEN_WIDTH (1U) 457 #define ADC_SC1N_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_AIEN_SHIFT)) & ADC_SC1N_AIEN_MASK) 458 459 #define ADC_SC1N_COCO_MASK (0x80U) 460 #define ADC_SC1N_COCO_SHIFT (7U) 461 #define ADC_SC1N_COCO_WIDTH (1U) 462 #define ADC_SC1N_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1N_COCO_SHIFT)) & ADC_SC1N_COCO_MASK) 463 /*! @} */ 464 465 /*! @name SC1O - ADC Status and Control Register 1 */ 466 /*! @{ */ 467 468 #define ADC_SC1O_ADCH_MASK (0x3FU) 469 #define ADC_SC1O_ADCH_SHIFT (0U) 470 #define ADC_SC1O_ADCH_WIDTH (6U) 471 #define ADC_SC1O_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_ADCH_SHIFT)) & ADC_SC1O_ADCH_MASK) 472 473 #define ADC_SC1O_AIEN_MASK (0x40U) 474 #define ADC_SC1O_AIEN_SHIFT (6U) 475 #define ADC_SC1O_AIEN_WIDTH (1U) 476 #define ADC_SC1O_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_AIEN_SHIFT)) & ADC_SC1O_AIEN_MASK) 477 478 #define ADC_SC1O_COCO_MASK (0x80U) 479 #define ADC_SC1O_COCO_SHIFT (7U) 480 #define ADC_SC1O_COCO_WIDTH (1U) 481 #define ADC_SC1O_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1O_COCO_SHIFT)) & ADC_SC1O_COCO_MASK) 482 /*! @} */ 483 484 /*! @name SC1P - ADC Status and Control Register 1 */ 485 /*! @{ */ 486 487 #define ADC_SC1P_ADCH_MASK (0x3FU) 488 #define ADC_SC1P_ADCH_SHIFT (0U) 489 #define ADC_SC1P_ADCH_WIDTH (6U) 490 #define ADC_SC1P_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_ADCH_SHIFT)) & ADC_SC1P_ADCH_MASK) 491 492 #define ADC_SC1P_AIEN_MASK (0x40U) 493 #define ADC_SC1P_AIEN_SHIFT (6U) 494 #define ADC_SC1P_AIEN_WIDTH (1U) 495 #define ADC_SC1P_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_AIEN_SHIFT)) & ADC_SC1P_AIEN_MASK) 496 497 #define ADC_SC1P_COCO_MASK (0x80U) 498 #define ADC_SC1P_COCO_SHIFT (7U) 499 #define ADC_SC1P_COCO_WIDTH (1U) 500 #define ADC_SC1P_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1P_COCO_SHIFT)) & ADC_SC1P_COCO_MASK) 501 /*! @} */ 502 503 /*! @name CFG1 - ADC Configuration Register 1 */ 504 /*! @{ */ 505 506 #define ADC_CFG1_ADICLK_MASK (0x3U) 507 #define ADC_CFG1_ADICLK_SHIFT (0U) 508 #define ADC_CFG1_ADICLK_WIDTH (2U) 509 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 510 511 #define ADC_CFG1_MODE_MASK (0xCU) 512 #define ADC_CFG1_MODE_SHIFT (2U) 513 #define ADC_CFG1_MODE_WIDTH (2U) 514 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 515 516 #define ADC_CFG1_ADIV_MASK (0x60U) 517 #define ADC_CFG1_ADIV_SHIFT (5U) 518 #define ADC_CFG1_ADIV_WIDTH (2U) 519 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 520 521 #define ADC_CFG1_CLRLTRG_MASK (0x100U) 522 #define ADC_CFG1_CLRLTRG_SHIFT (8U) 523 #define ADC_CFG1_CLRLTRG_WIDTH (1U) 524 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_CLRLTRG_SHIFT)) & ADC_CFG1_CLRLTRG_MASK) 525 /*! @} */ 526 527 /*! @name CFG2 - ADC Configuration Register 2 */ 528 /*! @{ */ 529 530 #define ADC_CFG2_SMPLTS_MASK (0xFFU) 531 #define ADC_CFG2_SMPLTS_SHIFT (0U) 532 #define ADC_CFG2_SMPLTS_WIDTH (8U) 533 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) 534 /*! @} */ 535 536 /*! @name RA - ADC Data Result Registers */ 537 /*! @{ */ 538 539 #define ADC_RA_D_MASK (0xFFFU) 540 #define ADC_RA_D_SHIFT (0U) 541 #define ADC_RA_D_WIDTH (12U) 542 #define ADC_RA_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RA_D_SHIFT)) & ADC_RA_D_MASK) 543 /*! @} */ 544 545 /*! @name RB - ADC Data Result Registers */ 546 /*! @{ */ 547 548 #define ADC_RB_D_MASK (0xFFFU) 549 #define ADC_RB_D_SHIFT (0U) 550 #define ADC_RB_D_WIDTH (12U) 551 #define ADC_RB_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RB_D_SHIFT)) & ADC_RB_D_MASK) 552 /*! @} */ 553 554 /*! @name RC - ADC Data Result Registers */ 555 /*! @{ */ 556 557 #define ADC_RC_D_MASK (0xFFFU) 558 #define ADC_RC_D_SHIFT (0U) 559 #define ADC_RC_D_WIDTH (12U) 560 #define ADC_RC_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RC_D_SHIFT)) & ADC_RC_D_MASK) 561 /*! @} */ 562 563 /*! @name RD - ADC Data Result Registers */ 564 /*! @{ */ 565 566 #define ADC_RD_D_MASK (0xFFFU) 567 #define ADC_RD_D_SHIFT (0U) 568 #define ADC_RD_D_WIDTH (12U) 569 #define ADC_RD_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RD_D_SHIFT)) & ADC_RD_D_MASK) 570 /*! @} */ 571 572 /*! @name RE - ADC Data Result Registers */ 573 /*! @{ */ 574 575 #define ADC_RE_D_MASK (0xFFFU) 576 #define ADC_RE_D_SHIFT (0U) 577 #define ADC_RE_D_WIDTH (12U) 578 #define ADC_RE_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RE_D_SHIFT)) & ADC_RE_D_MASK) 579 /*! @} */ 580 581 /*! @name RF - ADC Data Result Registers */ 582 /*! @{ */ 583 584 #define ADC_RF_D_MASK (0xFFFU) 585 #define ADC_RF_D_SHIFT (0U) 586 #define ADC_RF_D_WIDTH (12U) 587 #define ADC_RF_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RF_D_SHIFT)) & ADC_RF_D_MASK) 588 /*! @} */ 589 590 /*! @name RG - ADC Data Result Registers */ 591 /*! @{ */ 592 593 #define ADC_RG_D_MASK (0xFFFU) 594 #define ADC_RG_D_SHIFT (0U) 595 #define ADC_RG_D_WIDTH (12U) 596 #define ADC_RG_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RG_D_SHIFT)) & ADC_RG_D_MASK) 597 /*! @} */ 598 599 /*! @name RH - ADC Data Result Registers */ 600 /*! @{ */ 601 602 #define ADC_RH_D_MASK (0xFFFU) 603 #define ADC_RH_D_SHIFT (0U) 604 #define ADC_RH_D_WIDTH (12U) 605 #define ADC_RH_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RH_D_SHIFT)) & ADC_RH_D_MASK) 606 /*! @} */ 607 608 /*! @name RI - ADC Data Result Registers */ 609 /*! @{ */ 610 611 #define ADC_RI_D_MASK (0xFFFU) 612 #define ADC_RI_D_SHIFT (0U) 613 #define ADC_RI_D_WIDTH (12U) 614 #define ADC_RI_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RI_D_SHIFT)) & ADC_RI_D_MASK) 615 /*! @} */ 616 617 /*! @name RJ - ADC Data Result Registers */ 618 /*! @{ */ 619 620 #define ADC_RJ_D_MASK (0xFFFU) 621 #define ADC_RJ_D_SHIFT (0U) 622 #define ADC_RJ_D_WIDTH (12U) 623 #define ADC_RJ_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RJ_D_SHIFT)) & ADC_RJ_D_MASK) 624 /*! @} */ 625 626 /*! @name RK - ADC Data Result Registers */ 627 /*! @{ */ 628 629 #define ADC_RK_D_MASK (0xFFFU) 630 #define ADC_RK_D_SHIFT (0U) 631 #define ADC_RK_D_WIDTH (12U) 632 #define ADC_RK_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RK_D_SHIFT)) & ADC_RK_D_MASK) 633 /*! @} */ 634 635 /*! @name RL - ADC Data Result Registers */ 636 /*! @{ */ 637 638 #define ADC_RL_D_MASK (0xFFFU) 639 #define ADC_RL_D_SHIFT (0U) 640 #define ADC_RL_D_WIDTH (12U) 641 #define ADC_RL_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RL_D_SHIFT)) & ADC_RL_D_MASK) 642 /*! @} */ 643 644 /*! @name RM - ADC Data Result Registers */ 645 /*! @{ */ 646 647 #define ADC_RM_D_MASK (0xFFFU) 648 #define ADC_RM_D_SHIFT (0U) 649 #define ADC_RM_D_WIDTH (12U) 650 #define ADC_RM_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RM_D_SHIFT)) & ADC_RM_D_MASK) 651 /*! @} */ 652 653 /*! @name RN - ADC Data Result Registers */ 654 /*! @{ */ 655 656 #define ADC_RN_D_MASK (0xFFFU) 657 #define ADC_RN_D_SHIFT (0U) 658 #define ADC_RN_D_WIDTH (12U) 659 #define ADC_RN_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RN_D_SHIFT)) & ADC_RN_D_MASK) 660 /*! @} */ 661 662 /*! @name RO - ADC Data Result Registers */ 663 /*! @{ */ 664 665 #define ADC_RO_D_MASK (0xFFFU) 666 #define ADC_RO_D_SHIFT (0U) 667 #define ADC_RO_D_WIDTH (12U) 668 #define ADC_RO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RO_D_SHIFT)) & ADC_RO_D_MASK) 669 /*! @} */ 670 671 /*! @name RP - ADC Data Result Registers */ 672 /*! @{ */ 673 674 #define ADC_RP_D_MASK (0xFFFU) 675 #define ADC_RP_D_SHIFT (0U) 676 #define ADC_RP_D_WIDTH (12U) 677 #define ADC_RP_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RP_D_SHIFT)) & ADC_RP_D_MASK) 678 /*! @} */ 679 680 /*! @name CV - Compare Value Registers */ 681 /*! @{ */ 682 683 #define ADC_CV_CV_MASK (0xFFFFU) 684 #define ADC_CV_CV_SHIFT (0U) 685 #define ADC_CV_CV_WIDTH (16U) 686 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 687 /*! @} */ 688 689 /*! @name SC2 - Status and Control Register 2 */ 690 /*! @{ */ 691 692 #define ADC_SC2_REFSEL_MASK (0x3U) 693 #define ADC_SC2_REFSEL_SHIFT (0U) 694 #define ADC_SC2_REFSEL_WIDTH (2U) 695 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 696 697 #define ADC_SC2_DMAEN_MASK (0x4U) 698 #define ADC_SC2_DMAEN_SHIFT (2U) 699 #define ADC_SC2_DMAEN_WIDTH (1U) 700 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 701 702 #define ADC_SC2_ACREN_MASK (0x8U) 703 #define ADC_SC2_ACREN_SHIFT (3U) 704 #define ADC_SC2_ACREN_WIDTH (1U) 705 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 706 707 #define ADC_SC2_ACFGT_MASK (0x10U) 708 #define ADC_SC2_ACFGT_SHIFT (4U) 709 #define ADC_SC2_ACFGT_WIDTH (1U) 710 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 711 712 #define ADC_SC2_ACFE_MASK (0x20U) 713 #define ADC_SC2_ACFE_SHIFT (5U) 714 #define ADC_SC2_ACFE_WIDTH (1U) 715 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 716 717 #define ADC_SC2_ADTRG_MASK (0x40U) 718 #define ADC_SC2_ADTRG_SHIFT (6U) 719 #define ADC_SC2_ADTRG_WIDTH (1U) 720 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 721 722 #define ADC_SC2_ADACT_MASK (0x80U) 723 #define ADC_SC2_ADACT_SHIFT (7U) 724 #define ADC_SC2_ADACT_WIDTH (1U) 725 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 726 727 #define ADC_SC2_TRGPRNUM_MASK (0x6000U) 728 #define ADC_SC2_TRGPRNUM_SHIFT (13U) 729 #define ADC_SC2_TRGPRNUM_WIDTH (2U) 730 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGPRNUM_SHIFT)) & ADC_SC2_TRGPRNUM_MASK) 731 732 #define ADC_SC2_TRGSTLAT_MASK (0xF0000U) 733 #define ADC_SC2_TRGSTLAT_SHIFT (16U) 734 #define ADC_SC2_TRGSTLAT_WIDTH (4U) 735 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTLAT_SHIFT)) & ADC_SC2_TRGSTLAT_MASK) 736 737 #define ADC_SC2_TRGSTERR_MASK (0xF000000U) 738 #define ADC_SC2_TRGSTERR_SHIFT (24U) 739 #define ADC_SC2_TRGSTERR_WIDTH (4U) 740 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTERR_SHIFT)) & ADC_SC2_TRGSTERR_MASK) 741 /*! @} */ 742 743 /*! @name SC3 - Status and Control Register 3 */ 744 /*! @{ */ 745 746 #define ADC_SC3_AVGS_MASK (0x3U) 747 #define ADC_SC3_AVGS_SHIFT (0U) 748 #define ADC_SC3_AVGS_WIDTH (2U) 749 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 750 751 #define ADC_SC3_AVGE_MASK (0x4U) 752 #define ADC_SC3_AVGE_SHIFT (2U) 753 #define ADC_SC3_AVGE_WIDTH (1U) 754 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 755 756 #define ADC_SC3_ADCO_MASK (0x8U) 757 #define ADC_SC3_ADCO_SHIFT (3U) 758 #define ADC_SC3_ADCO_WIDTH (1U) 759 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 760 761 #define ADC_SC3_CAL_MASK (0x80U) 762 #define ADC_SC3_CAL_SHIFT (7U) 763 #define ADC_SC3_CAL_WIDTH (1U) 764 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 765 /*! @} */ 766 767 /*! @name BASE_OFS - BASE Offset Register */ 768 /*! @{ */ 769 770 #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) 771 #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) 772 #define ADC_BASE_OFS_BA_OFS_WIDTH (8U) 773 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) 774 /*! @} */ 775 776 /*! @name OFS - ADC Offset Correction Register */ 777 /*! @{ */ 778 779 #define ADC_OFS_OFS_MASK (0xFFFFU) 780 #define ADC_OFS_OFS_SHIFT (0U) 781 #define ADC_OFS_OFS_WIDTH (16U) 782 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 783 /*! @} */ 784 785 /*! @name USR_OFS - USER Offset Correction Register */ 786 /*! @{ */ 787 788 #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) 789 #define ADC_USR_OFS_USR_OFS_SHIFT (0U) 790 #define ADC_USR_OFS_USR_OFS_WIDTH (8U) 791 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) 792 /*! @} */ 793 794 /*! @name XOFS - ADC X Offset Correction Register */ 795 /*! @{ */ 796 797 #define ADC_XOFS_XOFS_MASK (0x3FU) 798 #define ADC_XOFS_XOFS_SHIFT (0U) 799 #define ADC_XOFS_XOFS_WIDTH (6U) 800 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) 801 /*! @} */ 802 803 /*! @name YOFS - ADC Y Offset Correction Register */ 804 /*! @{ */ 805 806 #define ADC_YOFS_YOFS_MASK (0xFFU) 807 #define ADC_YOFS_YOFS_SHIFT (0U) 808 #define ADC_YOFS_YOFS_WIDTH (8U) 809 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) 810 /*! @} */ 811 812 /*! @name G - ADC Gain Register */ 813 /*! @{ */ 814 815 #define ADC_G_G_MASK (0x7FFU) 816 #define ADC_G_G_SHIFT (0U) 817 #define ADC_G_G_WIDTH (11U) 818 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) 819 /*! @} */ 820 821 /*! @name UG - ADC User Gain Register */ 822 /*! @{ */ 823 824 #define ADC_UG_UG_MASK (0x3FFU) 825 #define ADC_UG_UG_SHIFT (0U) 826 #define ADC_UG_UG_WIDTH (10U) 827 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) 828 /*! @} */ 829 830 /*! @name CLPS - ADC General Calibration Value Register S */ 831 /*! @{ */ 832 833 #define ADC_CLPS_CLPS_MASK (0x7FU) 834 #define ADC_CLPS_CLPS_SHIFT (0U) 835 #define ADC_CLPS_CLPS_WIDTH (7U) 836 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 837 /*! @} */ 838 839 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ 840 /*! @{ */ 841 842 #define ADC_CLP3_CLP3_MASK (0x3FFU) 843 #define ADC_CLP3_CLP3_SHIFT (0U) 844 #define ADC_CLP3_CLP3_WIDTH (10U) 845 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 846 /*! @} */ 847 848 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ 849 /*! @{ */ 850 851 #define ADC_CLP2_CLP2_MASK (0x3FFU) 852 #define ADC_CLP2_CLP2_SHIFT (0U) 853 #define ADC_CLP2_CLP2_WIDTH (10U) 854 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 855 /*! @} */ 856 857 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ 858 /*! @{ */ 859 860 #define ADC_CLP1_CLP1_MASK (0x1FFU) 861 #define ADC_CLP1_CLP1_SHIFT (0U) 862 #define ADC_CLP1_CLP1_WIDTH (9U) 863 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 864 /*! @} */ 865 866 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ 867 /*! @{ */ 868 869 #define ADC_CLP0_CLP0_MASK (0xFFU) 870 #define ADC_CLP0_CLP0_SHIFT (0U) 871 #define ADC_CLP0_CLP0_WIDTH (8U) 872 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 873 /*! @} */ 874 875 /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ 876 /*! @{ */ 877 878 #define ADC_CLPX_CLPX_MASK (0x7FU) 879 #define ADC_CLPX_CLPX_SHIFT (0U) 880 #define ADC_CLPX_CLPX_WIDTH (7U) 881 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) 882 /*! @} */ 883 884 /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ 885 /*! @{ */ 886 887 #define ADC_CLP9_CLP9_MASK (0x7FU) 888 #define ADC_CLP9_CLP9_SHIFT (0U) 889 #define ADC_CLP9_CLP9_WIDTH (7U) 890 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) 891 /*! @} */ 892 893 /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ 894 /*! @{ */ 895 896 #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) 897 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) 898 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH (4U) 899 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) 900 /*! @} */ 901 902 /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ 903 /*! @{ */ 904 905 #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) 906 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) 907 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH (4U) 908 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) 909 /*! @} */ 910 911 /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ 912 /*! @{ */ 913 914 #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) 915 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) 916 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH (4U) 917 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) 918 /*! @} */ 919 920 /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ 921 /*! @{ */ 922 923 #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) 924 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) 925 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH (4U) 926 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) 927 /*! @} */ 928 929 /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ 930 /*! @{ */ 931 932 #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) 933 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) 934 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH (4U) 935 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) 936 /*! @} */ 937 938 /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ 939 /*! @{ */ 940 941 #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) 942 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) 943 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH (12U) 944 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) 945 /*! @} */ 946 947 /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ 948 /*! @{ */ 949 950 #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) 951 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) 952 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH (12U) 953 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) 954 /*! @} */ 955 956 /*! @name ASC1A - ADC Status and Control Register 1 */ 957 /*! @{ */ 958 959 #define ADC_ASC1A_ADCH_MASK (0x3FU) 960 #define ADC_ASC1A_ADCH_SHIFT (0U) 961 #define ADC_ASC1A_ADCH_WIDTH (6U) 962 #define ADC_ASC1A_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1A_ADCH_SHIFT)) & ADC_ASC1A_ADCH_MASK) 963 964 #define ADC_ASC1A_AIEN_MASK (0x40U) 965 #define ADC_ASC1A_AIEN_SHIFT (6U) 966 #define ADC_ASC1A_AIEN_WIDTH (1U) 967 #define ADC_ASC1A_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1A_AIEN_SHIFT)) & ADC_ASC1A_AIEN_MASK) 968 969 #define ADC_ASC1A_COCO_MASK (0x80U) 970 #define ADC_ASC1A_COCO_SHIFT (7U) 971 #define ADC_ASC1A_COCO_WIDTH (1U) 972 #define ADC_ASC1A_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1A_COCO_SHIFT)) & ADC_ASC1A_COCO_MASK) 973 /*! @} */ 974 975 /*! @name ASC1B - ADC Status and Control Register 1 */ 976 /*! @{ */ 977 978 #define ADC_ASC1B_ADCH_MASK (0x3FU) 979 #define ADC_ASC1B_ADCH_SHIFT (0U) 980 #define ADC_ASC1B_ADCH_WIDTH (6U) 981 #define ADC_ASC1B_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1B_ADCH_SHIFT)) & ADC_ASC1B_ADCH_MASK) 982 983 #define ADC_ASC1B_AIEN_MASK (0x40U) 984 #define ADC_ASC1B_AIEN_SHIFT (6U) 985 #define ADC_ASC1B_AIEN_WIDTH (1U) 986 #define ADC_ASC1B_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1B_AIEN_SHIFT)) & ADC_ASC1B_AIEN_MASK) 987 988 #define ADC_ASC1B_COCO_MASK (0x80U) 989 #define ADC_ASC1B_COCO_SHIFT (7U) 990 #define ADC_ASC1B_COCO_WIDTH (1U) 991 #define ADC_ASC1B_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1B_COCO_SHIFT)) & ADC_ASC1B_COCO_MASK) 992 /*! @} */ 993 994 /*! @name ASC1C - ADC Status and Control Register 1 */ 995 /*! @{ */ 996 997 #define ADC_ASC1C_ADCH_MASK (0x3FU) 998 #define ADC_ASC1C_ADCH_SHIFT (0U) 999 #define ADC_ASC1C_ADCH_WIDTH (6U) 1000 #define ADC_ASC1C_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1C_ADCH_SHIFT)) & ADC_ASC1C_ADCH_MASK) 1001 1002 #define ADC_ASC1C_AIEN_MASK (0x40U) 1003 #define ADC_ASC1C_AIEN_SHIFT (6U) 1004 #define ADC_ASC1C_AIEN_WIDTH (1U) 1005 #define ADC_ASC1C_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1C_AIEN_SHIFT)) & ADC_ASC1C_AIEN_MASK) 1006 1007 #define ADC_ASC1C_COCO_MASK (0x80U) 1008 #define ADC_ASC1C_COCO_SHIFT (7U) 1009 #define ADC_ASC1C_COCO_WIDTH (1U) 1010 #define ADC_ASC1C_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1C_COCO_SHIFT)) & ADC_ASC1C_COCO_MASK) 1011 /*! @} */ 1012 1013 /*! @name ASC1D - ADC Status and Control Register 1 */ 1014 /*! @{ */ 1015 1016 #define ADC_ASC1D_ADCH_MASK (0x3FU) 1017 #define ADC_ASC1D_ADCH_SHIFT (0U) 1018 #define ADC_ASC1D_ADCH_WIDTH (6U) 1019 #define ADC_ASC1D_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1D_ADCH_SHIFT)) & ADC_ASC1D_ADCH_MASK) 1020 1021 #define ADC_ASC1D_AIEN_MASK (0x40U) 1022 #define ADC_ASC1D_AIEN_SHIFT (6U) 1023 #define ADC_ASC1D_AIEN_WIDTH (1U) 1024 #define ADC_ASC1D_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1D_AIEN_SHIFT)) & ADC_ASC1D_AIEN_MASK) 1025 1026 #define ADC_ASC1D_COCO_MASK (0x80U) 1027 #define ADC_ASC1D_COCO_SHIFT (7U) 1028 #define ADC_ASC1D_COCO_WIDTH (1U) 1029 #define ADC_ASC1D_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1D_COCO_SHIFT)) & ADC_ASC1D_COCO_MASK) 1030 /*! @} */ 1031 1032 /*! @name ASC1E - ADC Status and Control Register 1 */ 1033 /*! @{ */ 1034 1035 #define ADC_ASC1E_ADCH_MASK (0x3FU) 1036 #define ADC_ASC1E_ADCH_SHIFT (0U) 1037 #define ADC_ASC1E_ADCH_WIDTH (6U) 1038 #define ADC_ASC1E_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1E_ADCH_SHIFT)) & ADC_ASC1E_ADCH_MASK) 1039 1040 #define ADC_ASC1E_AIEN_MASK (0x40U) 1041 #define ADC_ASC1E_AIEN_SHIFT (6U) 1042 #define ADC_ASC1E_AIEN_WIDTH (1U) 1043 #define ADC_ASC1E_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1E_AIEN_SHIFT)) & ADC_ASC1E_AIEN_MASK) 1044 1045 #define ADC_ASC1E_COCO_MASK (0x80U) 1046 #define ADC_ASC1E_COCO_SHIFT (7U) 1047 #define ADC_ASC1E_COCO_WIDTH (1U) 1048 #define ADC_ASC1E_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1E_COCO_SHIFT)) & ADC_ASC1E_COCO_MASK) 1049 /*! @} */ 1050 1051 /*! @name ASC1F - ADC Status and Control Register 1 */ 1052 /*! @{ */ 1053 1054 #define ADC_ASC1F_ADCH_MASK (0x3FU) 1055 #define ADC_ASC1F_ADCH_SHIFT (0U) 1056 #define ADC_ASC1F_ADCH_WIDTH (6U) 1057 #define ADC_ASC1F_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1F_ADCH_SHIFT)) & ADC_ASC1F_ADCH_MASK) 1058 1059 #define ADC_ASC1F_AIEN_MASK (0x40U) 1060 #define ADC_ASC1F_AIEN_SHIFT (6U) 1061 #define ADC_ASC1F_AIEN_WIDTH (1U) 1062 #define ADC_ASC1F_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1F_AIEN_SHIFT)) & ADC_ASC1F_AIEN_MASK) 1063 1064 #define ADC_ASC1F_COCO_MASK (0x80U) 1065 #define ADC_ASC1F_COCO_SHIFT (7U) 1066 #define ADC_ASC1F_COCO_WIDTH (1U) 1067 #define ADC_ASC1F_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1F_COCO_SHIFT)) & ADC_ASC1F_COCO_MASK) 1068 /*! @} */ 1069 1070 /*! @name ASC1G - ADC Status and Control Register 1 */ 1071 /*! @{ */ 1072 1073 #define ADC_ASC1G_ADCH_MASK (0x3FU) 1074 #define ADC_ASC1G_ADCH_SHIFT (0U) 1075 #define ADC_ASC1G_ADCH_WIDTH (6U) 1076 #define ADC_ASC1G_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1G_ADCH_SHIFT)) & ADC_ASC1G_ADCH_MASK) 1077 1078 #define ADC_ASC1G_AIEN_MASK (0x40U) 1079 #define ADC_ASC1G_AIEN_SHIFT (6U) 1080 #define ADC_ASC1G_AIEN_WIDTH (1U) 1081 #define ADC_ASC1G_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1G_AIEN_SHIFT)) & ADC_ASC1G_AIEN_MASK) 1082 1083 #define ADC_ASC1G_COCO_MASK (0x80U) 1084 #define ADC_ASC1G_COCO_SHIFT (7U) 1085 #define ADC_ASC1G_COCO_WIDTH (1U) 1086 #define ADC_ASC1G_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1G_COCO_SHIFT)) & ADC_ASC1G_COCO_MASK) 1087 /*! @} */ 1088 1089 /*! @name ASC1H - ADC Status and Control Register 1 */ 1090 /*! @{ */ 1091 1092 #define ADC_ASC1H_ADCH_MASK (0x3FU) 1093 #define ADC_ASC1H_ADCH_SHIFT (0U) 1094 #define ADC_ASC1H_ADCH_WIDTH (6U) 1095 #define ADC_ASC1H_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1H_ADCH_SHIFT)) & ADC_ASC1H_ADCH_MASK) 1096 1097 #define ADC_ASC1H_AIEN_MASK (0x40U) 1098 #define ADC_ASC1H_AIEN_SHIFT (6U) 1099 #define ADC_ASC1H_AIEN_WIDTH (1U) 1100 #define ADC_ASC1H_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1H_AIEN_SHIFT)) & ADC_ASC1H_AIEN_MASK) 1101 1102 #define ADC_ASC1H_COCO_MASK (0x80U) 1103 #define ADC_ASC1H_COCO_SHIFT (7U) 1104 #define ADC_ASC1H_COCO_WIDTH (1U) 1105 #define ADC_ASC1H_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1H_COCO_SHIFT)) & ADC_ASC1H_COCO_MASK) 1106 /*! @} */ 1107 1108 /*! @name ASC1I - ADC Status and Control Register 1 */ 1109 /*! @{ */ 1110 1111 #define ADC_ASC1I_ADCH_MASK (0x3FU) 1112 #define ADC_ASC1I_ADCH_SHIFT (0U) 1113 #define ADC_ASC1I_ADCH_WIDTH (6U) 1114 #define ADC_ASC1I_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1I_ADCH_SHIFT)) & ADC_ASC1I_ADCH_MASK) 1115 1116 #define ADC_ASC1I_AIEN_MASK (0x40U) 1117 #define ADC_ASC1I_AIEN_SHIFT (6U) 1118 #define ADC_ASC1I_AIEN_WIDTH (1U) 1119 #define ADC_ASC1I_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1I_AIEN_SHIFT)) & ADC_ASC1I_AIEN_MASK) 1120 1121 #define ADC_ASC1I_COCO_MASK (0x80U) 1122 #define ADC_ASC1I_COCO_SHIFT (7U) 1123 #define ADC_ASC1I_COCO_WIDTH (1U) 1124 #define ADC_ASC1I_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1I_COCO_SHIFT)) & ADC_ASC1I_COCO_MASK) 1125 /*! @} */ 1126 1127 /*! @name ASC1J - ADC Status and Control Register 1 */ 1128 /*! @{ */ 1129 1130 #define ADC_ASC1J_ADCH_MASK (0x3FU) 1131 #define ADC_ASC1J_ADCH_SHIFT (0U) 1132 #define ADC_ASC1J_ADCH_WIDTH (6U) 1133 #define ADC_ASC1J_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1J_ADCH_SHIFT)) & ADC_ASC1J_ADCH_MASK) 1134 1135 #define ADC_ASC1J_AIEN_MASK (0x40U) 1136 #define ADC_ASC1J_AIEN_SHIFT (6U) 1137 #define ADC_ASC1J_AIEN_WIDTH (1U) 1138 #define ADC_ASC1J_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1J_AIEN_SHIFT)) & ADC_ASC1J_AIEN_MASK) 1139 1140 #define ADC_ASC1J_COCO_MASK (0x80U) 1141 #define ADC_ASC1J_COCO_SHIFT (7U) 1142 #define ADC_ASC1J_COCO_WIDTH (1U) 1143 #define ADC_ASC1J_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1J_COCO_SHIFT)) & ADC_ASC1J_COCO_MASK) 1144 /*! @} */ 1145 1146 /*! @name ASC1K - ADC Status and Control Register 1 */ 1147 /*! @{ */ 1148 1149 #define ADC_ASC1K_ADCH_MASK (0x3FU) 1150 #define ADC_ASC1K_ADCH_SHIFT (0U) 1151 #define ADC_ASC1K_ADCH_WIDTH (6U) 1152 #define ADC_ASC1K_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1K_ADCH_SHIFT)) & ADC_ASC1K_ADCH_MASK) 1153 1154 #define ADC_ASC1K_AIEN_MASK (0x40U) 1155 #define ADC_ASC1K_AIEN_SHIFT (6U) 1156 #define ADC_ASC1K_AIEN_WIDTH (1U) 1157 #define ADC_ASC1K_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1K_AIEN_SHIFT)) & ADC_ASC1K_AIEN_MASK) 1158 1159 #define ADC_ASC1K_COCO_MASK (0x80U) 1160 #define ADC_ASC1K_COCO_SHIFT (7U) 1161 #define ADC_ASC1K_COCO_WIDTH (1U) 1162 #define ADC_ASC1K_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1K_COCO_SHIFT)) & ADC_ASC1K_COCO_MASK) 1163 /*! @} */ 1164 1165 /*! @name ASC1L - ADC Status and Control Register 1 */ 1166 /*! @{ */ 1167 1168 #define ADC_ASC1L_ADCH_MASK (0x3FU) 1169 #define ADC_ASC1L_ADCH_SHIFT (0U) 1170 #define ADC_ASC1L_ADCH_WIDTH (6U) 1171 #define ADC_ASC1L_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1L_ADCH_SHIFT)) & ADC_ASC1L_ADCH_MASK) 1172 1173 #define ADC_ASC1L_AIEN_MASK (0x40U) 1174 #define ADC_ASC1L_AIEN_SHIFT (6U) 1175 #define ADC_ASC1L_AIEN_WIDTH (1U) 1176 #define ADC_ASC1L_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1L_AIEN_SHIFT)) & ADC_ASC1L_AIEN_MASK) 1177 1178 #define ADC_ASC1L_COCO_MASK (0x80U) 1179 #define ADC_ASC1L_COCO_SHIFT (7U) 1180 #define ADC_ASC1L_COCO_WIDTH (1U) 1181 #define ADC_ASC1L_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1L_COCO_SHIFT)) & ADC_ASC1L_COCO_MASK) 1182 /*! @} */ 1183 1184 /*! @name ASC1M - ADC Status and Control Register 1 */ 1185 /*! @{ */ 1186 1187 #define ADC_ASC1M_ADCH_MASK (0x3FU) 1188 #define ADC_ASC1M_ADCH_SHIFT (0U) 1189 #define ADC_ASC1M_ADCH_WIDTH (6U) 1190 #define ADC_ASC1M_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1M_ADCH_SHIFT)) & ADC_ASC1M_ADCH_MASK) 1191 1192 #define ADC_ASC1M_AIEN_MASK (0x40U) 1193 #define ADC_ASC1M_AIEN_SHIFT (6U) 1194 #define ADC_ASC1M_AIEN_WIDTH (1U) 1195 #define ADC_ASC1M_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1M_AIEN_SHIFT)) & ADC_ASC1M_AIEN_MASK) 1196 1197 #define ADC_ASC1M_COCO_MASK (0x80U) 1198 #define ADC_ASC1M_COCO_SHIFT (7U) 1199 #define ADC_ASC1M_COCO_WIDTH (1U) 1200 #define ADC_ASC1M_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1M_COCO_SHIFT)) & ADC_ASC1M_COCO_MASK) 1201 /*! @} */ 1202 1203 /*! @name ASC1N - ADC Status and Control Register 1 */ 1204 /*! @{ */ 1205 1206 #define ADC_ASC1N_ADCH_MASK (0x3FU) 1207 #define ADC_ASC1N_ADCH_SHIFT (0U) 1208 #define ADC_ASC1N_ADCH_WIDTH (6U) 1209 #define ADC_ASC1N_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1N_ADCH_SHIFT)) & ADC_ASC1N_ADCH_MASK) 1210 1211 #define ADC_ASC1N_AIEN_MASK (0x40U) 1212 #define ADC_ASC1N_AIEN_SHIFT (6U) 1213 #define ADC_ASC1N_AIEN_WIDTH (1U) 1214 #define ADC_ASC1N_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1N_AIEN_SHIFT)) & ADC_ASC1N_AIEN_MASK) 1215 1216 #define ADC_ASC1N_COCO_MASK (0x80U) 1217 #define ADC_ASC1N_COCO_SHIFT (7U) 1218 #define ADC_ASC1N_COCO_WIDTH (1U) 1219 #define ADC_ASC1N_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1N_COCO_SHIFT)) & ADC_ASC1N_COCO_MASK) 1220 /*! @} */ 1221 1222 /*! @name ASC1O - ADC Status and Control Register 1 */ 1223 /*! @{ */ 1224 1225 #define ADC_ASC1O_ADCH_MASK (0x3FU) 1226 #define ADC_ASC1O_ADCH_SHIFT (0U) 1227 #define ADC_ASC1O_ADCH_WIDTH (6U) 1228 #define ADC_ASC1O_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1O_ADCH_SHIFT)) & ADC_ASC1O_ADCH_MASK) 1229 1230 #define ADC_ASC1O_AIEN_MASK (0x40U) 1231 #define ADC_ASC1O_AIEN_SHIFT (6U) 1232 #define ADC_ASC1O_AIEN_WIDTH (1U) 1233 #define ADC_ASC1O_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1O_AIEN_SHIFT)) & ADC_ASC1O_AIEN_MASK) 1234 1235 #define ADC_ASC1O_COCO_MASK (0x80U) 1236 #define ADC_ASC1O_COCO_SHIFT (7U) 1237 #define ADC_ASC1O_COCO_WIDTH (1U) 1238 #define ADC_ASC1O_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1O_COCO_SHIFT)) & ADC_ASC1O_COCO_MASK) 1239 /*! @} */ 1240 1241 /*! @name ASC1P - ADC Status and Control Register 1 */ 1242 /*! @{ */ 1243 1244 #define ADC_ASC1P_ADCH_MASK (0x3FU) 1245 #define ADC_ASC1P_ADCH_SHIFT (0U) 1246 #define ADC_ASC1P_ADCH_WIDTH (6U) 1247 #define ADC_ASC1P_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1P_ADCH_SHIFT)) & ADC_ASC1P_ADCH_MASK) 1248 1249 #define ADC_ASC1P_AIEN_MASK (0x40U) 1250 #define ADC_ASC1P_AIEN_SHIFT (6U) 1251 #define ADC_ASC1P_AIEN_WIDTH (1U) 1252 #define ADC_ASC1P_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1P_AIEN_SHIFT)) & ADC_ASC1P_AIEN_MASK) 1253 1254 #define ADC_ASC1P_COCO_MASK (0x80U) 1255 #define ADC_ASC1P_COCO_SHIFT (7U) 1256 #define ADC_ASC1P_COCO_WIDTH (1U) 1257 #define ADC_ASC1P_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ASC1P_COCO_SHIFT)) & ADC_ASC1P_COCO_MASK) 1258 /*! @} */ 1259 1260 /*! @name SC1 - ADC Status and Control Register 1 */ 1261 /*! @{ */ 1262 1263 #define ADC_SC1_ADCH_MASK (0x3FU) 1264 #define ADC_SC1_ADCH_SHIFT (0U) 1265 #define ADC_SC1_ADCH_WIDTH (6U) 1266 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 1267 1268 #define ADC_SC1_AIEN_MASK (0x40U) 1269 #define ADC_SC1_AIEN_SHIFT (6U) 1270 #define ADC_SC1_AIEN_WIDTH (1U) 1271 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 1272 1273 #define ADC_SC1_COCO_MASK (0x80U) 1274 #define ADC_SC1_COCO_SHIFT (7U) 1275 #define ADC_SC1_COCO_WIDTH (1U) 1276 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 1277 /*! @} */ 1278 1279 /*! @name ARA - ADC Data Result Registers */ 1280 /*! @{ */ 1281 1282 #define ADC_ARA_D_MASK (0xFFFU) 1283 #define ADC_ARA_D_SHIFT (0U) 1284 #define ADC_ARA_D_WIDTH (12U) 1285 #define ADC_ARA_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARA_D_SHIFT)) & ADC_ARA_D_MASK) 1286 /*! @} */ 1287 1288 /*! @name ARB - ADC Data Result Registers */ 1289 /*! @{ */ 1290 1291 #define ADC_ARB_D_MASK (0xFFFU) 1292 #define ADC_ARB_D_SHIFT (0U) 1293 #define ADC_ARB_D_WIDTH (12U) 1294 #define ADC_ARB_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARB_D_SHIFT)) & ADC_ARB_D_MASK) 1295 /*! @} */ 1296 1297 /*! @name ARC - ADC Data Result Registers */ 1298 /*! @{ */ 1299 1300 #define ADC_ARC_D_MASK (0xFFFU) 1301 #define ADC_ARC_D_SHIFT (0U) 1302 #define ADC_ARC_D_WIDTH (12U) 1303 #define ADC_ARC_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARC_D_SHIFT)) & ADC_ARC_D_MASK) 1304 /*! @} */ 1305 1306 /*! @name ARD - ADC Data Result Registers */ 1307 /*! @{ */ 1308 1309 #define ADC_ARD_D_MASK (0xFFFU) 1310 #define ADC_ARD_D_SHIFT (0U) 1311 #define ADC_ARD_D_WIDTH (12U) 1312 #define ADC_ARD_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARD_D_SHIFT)) & ADC_ARD_D_MASK) 1313 /*! @} */ 1314 1315 /*! @name ARE - ADC Data Result Registers */ 1316 /*! @{ */ 1317 1318 #define ADC_ARE_D_MASK (0xFFFU) 1319 #define ADC_ARE_D_SHIFT (0U) 1320 #define ADC_ARE_D_WIDTH (12U) 1321 #define ADC_ARE_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARE_D_SHIFT)) & ADC_ARE_D_MASK) 1322 /*! @} */ 1323 1324 /*! @name ARF - ADC Data Result Registers */ 1325 /*! @{ */ 1326 1327 #define ADC_ARF_D_MASK (0xFFFU) 1328 #define ADC_ARF_D_SHIFT (0U) 1329 #define ADC_ARF_D_WIDTH (12U) 1330 #define ADC_ARF_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARF_D_SHIFT)) & ADC_ARF_D_MASK) 1331 /*! @} */ 1332 1333 /*! @name ARG - ADC Data Result Registers */ 1334 /*! @{ */ 1335 1336 #define ADC_ARG_D_MASK (0xFFFU) 1337 #define ADC_ARG_D_SHIFT (0U) 1338 #define ADC_ARG_D_WIDTH (12U) 1339 #define ADC_ARG_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARG_D_SHIFT)) & ADC_ARG_D_MASK) 1340 /*! @} */ 1341 1342 /*! @name ARH - ADC Data Result Registers */ 1343 /*! @{ */ 1344 1345 #define ADC_ARH_D_MASK (0xFFFU) 1346 #define ADC_ARH_D_SHIFT (0U) 1347 #define ADC_ARH_D_WIDTH (12U) 1348 #define ADC_ARH_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARH_D_SHIFT)) & ADC_ARH_D_MASK) 1349 /*! @} */ 1350 1351 /*! @name ARI - ADC Data Result Registers */ 1352 /*! @{ */ 1353 1354 #define ADC_ARI_D_MASK (0xFFFU) 1355 #define ADC_ARI_D_SHIFT (0U) 1356 #define ADC_ARI_D_WIDTH (12U) 1357 #define ADC_ARI_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARI_D_SHIFT)) & ADC_ARI_D_MASK) 1358 /*! @} */ 1359 1360 /*! @name ARJ - ADC Data Result Registers */ 1361 /*! @{ */ 1362 1363 #define ADC_ARJ_D_MASK (0xFFFU) 1364 #define ADC_ARJ_D_SHIFT (0U) 1365 #define ADC_ARJ_D_WIDTH (12U) 1366 #define ADC_ARJ_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARJ_D_SHIFT)) & ADC_ARJ_D_MASK) 1367 /*! @} */ 1368 1369 /*! @name ARK - ADC Data Result Registers */ 1370 /*! @{ */ 1371 1372 #define ADC_ARK_D_MASK (0xFFFU) 1373 #define ADC_ARK_D_SHIFT (0U) 1374 #define ADC_ARK_D_WIDTH (12U) 1375 #define ADC_ARK_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARK_D_SHIFT)) & ADC_ARK_D_MASK) 1376 /*! @} */ 1377 1378 /*! @name ARL - ADC Data Result Registers */ 1379 /*! @{ */ 1380 1381 #define ADC_ARL_D_MASK (0xFFFU) 1382 #define ADC_ARL_D_SHIFT (0U) 1383 #define ADC_ARL_D_WIDTH (12U) 1384 #define ADC_ARL_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARL_D_SHIFT)) & ADC_ARL_D_MASK) 1385 /*! @} */ 1386 1387 /*! @name ARM - ADC Data Result Registers */ 1388 /*! @{ */ 1389 1390 #define ADC_ARM_D_MASK (0xFFFU) 1391 #define ADC_ARM_D_SHIFT (0U) 1392 #define ADC_ARM_D_WIDTH (12U) 1393 #define ADC_ARM_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARM_D_SHIFT)) & ADC_ARM_D_MASK) 1394 /*! @} */ 1395 1396 /*! @name ARN - ADC Data Result Registers */ 1397 /*! @{ */ 1398 1399 #define ADC_ARN_D_MASK (0xFFFU) 1400 #define ADC_ARN_D_SHIFT (0U) 1401 #define ADC_ARN_D_WIDTH (12U) 1402 #define ADC_ARN_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARN_D_SHIFT)) & ADC_ARN_D_MASK) 1403 /*! @} */ 1404 1405 /*! @name ARO - ADC Data Result Registers */ 1406 /*! @{ */ 1407 1408 #define ADC_ARO_D_MASK (0xFFFU) 1409 #define ADC_ARO_D_SHIFT (0U) 1410 #define ADC_ARO_D_WIDTH (12U) 1411 #define ADC_ARO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARO_D_SHIFT)) & ADC_ARO_D_MASK) 1412 /*! @} */ 1413 1414 /*! @name ARP - ADC Data Result Registers */ 1415 /*! @{ */ 1416 1417 #define ADC_ARP_D_MASK (0xFFFU) 1418 #define ADC_ARP_D_SHIFT (0U) 1419 #define ADC_ARP_D_WIDTH (12U) 1420 #define ADC_ARP_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_ARP_D_SHIFT)) & ADC_ARP_D_MASK) 1421 /*! @} */ 1422 1423 /*! @name R - ADC Data Result Registers */ 1424 /*! @{ */ 1425 1426 #define ADC_R_D_MASK (0xFFFU) 1427 #define ADC_R_D_SHIFT (0U) 1428 #define ADC_R_D_WIDTH (12U) 1429 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 1430 /*! @} */ 1431 1432 /*! 1433 * @} 1434 */ /* end of group ADC_Register_Masks */ 1435 1436 /*! 1437 * @} 1438 */ /* end of group ADC_Peripheral_Access_Layer */ 1439 1440 #endif /* #if !defined(S32K148_ADC_H_) */ 1441
