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Searched refs:ACM_GPT5_CLK_SEL_SEL_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h849 #define ACM_GPT5_CLK_SEL_SEL_MASK (0x7U) macro
852 … (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK)
DMIMX8QM6_dsp.h809 #define ACM_GPT5_CLK_SEL_SEL_MASK (0x7U) macro
812 … (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK)
DMIMX8QM6_cm4_core1.h827 #define ACM_GPT5_CLK_SEL_SEL_MASK (0x7U) macro
829 … (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK)
DMIMX8QM6_cm4_core0.h827 #define ACM_GPT5_CLK_SEL_SEL_MASK (0x7U) macro
829 … (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK)