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Searched refs:A32KHZWAKECLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h596 #define A32KHZWAKECLKDIV_OFFSET 0x734 macro
971 …kCLOCK_Div32KhzWakeClk = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< Khz Wake Clk Divider…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h596 #define A32KHZWAKECLKDIV_OFFSET 0x734 macro
971 …kCLOCK_Div32KhzWakeClk = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< Khz Wake Clk Divider…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h596 #define A32KHZWAKECLKDIV_OFFSET 0x734 macro
971 …kCLOCK_Div32KhzWakeClk = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< Khz Wake Clk Divider…