1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_DMA_H_
10 #define FSL_DMA_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup dma
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*! @{ */
25 /*! @brief DMA driver version 2.1.2. */
26 #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
27 /*! @} */
28
29 /*! @brief _dma_channel_status_flags status flag for the DMA driver. */
30 enum
31 {
32 kDMA_TransactionsBCRFlag = DMA_DSR_BCR_BCR_MASK, /*!< Contains the number of bytes yet to be
33 transferred for a given block */
34 kDMA_TransactionsDoneFlag = DMA_DSR_BCR_DONE_MASK, /*!< Transactions Done */
35 kDMA_TransactionsBusyFlag = DMA_DSR_BCR_BSY_MASK, /*!< Transactions Busy */
36 kDMA_TransactionsRequestFlag = DMA_DSR_BCR_REQ_MASK, /*!< Transactions Request */
37 kDMA_BusErrorOnDestinationFlag = DMA_DSR_BCR_BED_MASK, /*!< Bus Error on Destination */
38 kDMA_BusErrorOnSourceFlag = DMA_DSR_BCR_BES_MASK, /*!< Bus Error on Source */
39 kDMA_ConfigurationErrorFlag = DMA_DSR_BCR_CE_MASK, /*!< Configuration Error */
40 };
41
42 /*! @brief DMA transfer size type*/
43 typedef enum _dma_transfer_size
44 {
45 kDMA_Transfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */
46 kDMA_Transfersize8bits, /*!< 8 bits are transferred for every read/write */
47 kDMA_Transfersize16bits, /*!< 16b its are transferred for every read/write */
48 } dma_transfer_size_t;
49
50 /*! @brief Configuration type for the DMA modulo */
51 typedef enum _dma_modulo
52 {
53 kDMA_ModuloDisable = 0x0U, /*!< Buffer disabled */
54 kDMA_Modulo16Bytes, /*!< Circular buffer size is 16 bytes. */
55 kDMA_Modulo32Bytes, /*!< Circular buffer size is 32 bytes. */
56 kDMA_Modulo64Bytes, /*!< Circular buffer size is 64 bytes. */
57 kDMA_Modulo128Bytes, /*!< Circular buffer size is 128 bytes. */
58 kDMA_Modulo256Bytes, /*!< Circular buffer size is 256 bytes. */
59 kDMA_Modulo512Bytes, /*!< Circular buffer size is 512 bytes. */
60 kDMA_Modulo1KBytes, /*!< Circular buffer size is 1 KB. */
61 kDMA_Modulo2KBytes, /*!< Circular buffer size is 2 KB. */
62 kDMA_Modulo4KBytes, /*!< Circular buffer size is 4 KB. */
63 kDMA_Modulo8KBytes, /*!< Circular buffer size is 8 KB. */
64 kDMA_Modulo16KBytes, /*!< Circular buffer size is 16 KB. */
65 kDMA_Modulo32KBytes, /*!< Circular buffer size is 32 KB. */
66 kDMA_Modulo64KBytes, /*!< Circular buffer size is 64 KB. */
67 kDMA_Modulo128KBytes, /*!< Circular buffer size is 128 KB. */
68 kDMA_Modulo256KBytes, /*!< Circular buffer size is 256 KB. */
69 } dma_modulo_t;
70
71 /*! @brief DMA channel link type */
72 typedef enum _dma_channel_link_type
73 {
74 kDMA_ChannelLinkDisable = 0x0U, /*!< No channel link. */
75 kDMA_ChannelLinkChannel1AndChannel2, /*!< Perform a link to channel LCH1 after each cycle-steal transfer.
76 followed by a link to LCH2 after the BCR decrements to 0. */
77 kDMA_ChannelLinkChannel1, /*!< Perform a link to LCH1 after each cycle-steal transfer. */
78 kDMA_ChannelLinkChannel1AfterBCR0, /*!< Perform a link to LCH1 after the BCR decrements. */
79 } dma_channel_link_type_t;
80
81 /*! @brief DMA transfer type */
82 typedef enum _dma_transfer_type
83 {
84 kDMA_MemoryToMemory = 0x0U, /*!< Memory to Memory transfer. */
85 kDMA_PeripheralToMemory, /*!< Peripheral to Memory transfer. */
86 kDMA_MemoryToPeripheral, /*!< Memory to Peripheral transfer. */
87 } dma_transfer_type_t;
88
89 /*! @brief DMA transfer options */
90 typedef enum _dma_transfer_options
91 {
92 kDMA_NoOptions = 0x0U, /*!< Transfer without options. */
93 kDMA_EnableInterrupt, /*!< Enable interrupt while transfer complete. */
94 } dma_transfer_options_t;
95
96 /*! @brief dma addre increment type */
97 typedef enum _dma_addr_increment
98 {
99 kDMA_AddrNoIncrement = 0x0U, /*!< Transfer address not increment. */
100 kDMA_AddrIncrementPerTransferWidth = 0x1U, /*!< Transfer address increment per transfer width */
101 } dma_addr_increment_t;
102
103 /*! @brief _dma_transfer_status DMA transfer status */
104 enum
105 {
106 kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< DMA is busy. */
107 };
108
109 /*! @brief DMA transfer configuration structure */
110 typedef struct _dma_transfer_config
111 {
112 uint32_t srcAddr; /*!< DMA transfer source address. */
113 uint32_t destAddr; /*!< DMA destination address.*/
114 bool enableSrcIncrement; /*!< Source address increase after each transfer. */
115 dma_transfer_size_t srcSize; /*!< Source transfer size unit. */
116 bool enableDestIncrement; /*!< Destination address increase after each transfer. */
117 dma_transfer_size_t destSize; /*!< Destination transfer unit.*/
118 uint32_t transferSize; /*!< The number of bytes to be transferred. */
119 } dma_transfer_config_t;
120
121 /*! @brief DMA transfer configuration structure */
122 typedef struct _dma_channel_link_config
123 {
124 dma_channel_link_type_t linkType; /*!< Channel link type. */
125 uint32_t channel1; /*!< The index of channel 1. */
126 uint32_t channel2; /*!< The index of channel 2. */
127 } dma_channel_link_config_t;
128
129 struct _dma_handle;
130 /*! @brief Callback function prototype for the DMA driver. */
131 typedef void (*dma_callback)(struct _dma_handle *handle, void *userData);
132
133 /*! @brief DMA DMA handle structure */
134 typedef struct _dma_handle
135 {
136 DMA_Type *base; /*!< DMA peripheral address. */
137 uint8_t channel; /*!< DMA channel used. */
138 dma_callback callback; /*!< DMA callback function.*/
139 void *userData; /*!< Callback parameter. */
140 } dma_handle_t;
141
142 /*******************************************************************************
143 * API
144 ******************************************************************************/
145 #if defined(__cplusplus)
146 extern "C" {
147 #endif /* __cplusplus */
148
149 /*!
150 * @name DMA Initialization and De-initialization
151 * @{
152 */
153
154 /*!
155 * @brief Initializes the DMA peripheral.
156 *
157 * This function ungates the DMA clock.
158 *
159 * @param base DMA peripheral base address.
160 */
161 void DMA_Init(DMA_Type *base);
162
163 /*!
164 * @brief Deinitializes the DMA peripheral.
165 *
166 * This function gates the DMA clock.
167 *
168 * @param base DMA peripheral base address.
169 */
170 void DMA_Deinit(DMA_Type *base);
171
172 /*! @} */
173 /*!
174 * @name DMA Channel Operation
175 * @{
176 */
177
178 /*!
179 * @brief Resets the DMA channel.
180 *
181 * Sets all register values to reset values and enables
182 * the cycle steal and auto stop channel request features.
183 *
184 * @param base DMA peripheral base address.
185 * @param channel DMA channel number.
186 */
187 void DMA_ResetChannel(DMA_Type *base, uint32_t channel);
188
189 /*!
190 * @brief Configures the DMA transfer attribute.
191 *
192 * This function configures the transfer attribute including the source address,
193 * destination address, transfer size, and so on.
194 * This example shows how to set up the dma_transfer_config_t
195 * parameters and how to call the DMA_ConfigBasicTransfer function.
196 * @code
197 * dma_transfer_config_t transferConfig;
198 * memset(&transferConfig, 0, sizeof(transferConfig));
199 * transferConfig.srcAddr = (uint32_t)srcAddr;
200 * transferConfig.destAddr = (uint32_t)destAddr;
201 * transferConfig.enbaleSrcIncrement = true;
202 * transferConfig.enableDestIncrement = true;
203 * transferConfig.srcSize = kDMA_Transfersize32bits;
204 * transferConfig.destSize = kDMA_Transfersize32bits;
205 * transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH;
206 * DMA_SetTransferConfig(DMA0, 0, &transferConfig);
207 * @endcode
208 *
209 * @param base DMA peripheral base address.
210 * @param channel DMA channel number.
211 * @param config Pointer to the DMA transfer configuration structure.
212 */
213 void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config);
214
215 /*!
216 * @brief Configures the DMA channel link feature.
217 *
218 * This function allows DMA channels to have their transfers linked. The current DMA channel
219 * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link
220 * type.
221 * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2
222 * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2.
223 * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1.
224 * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0.
225 *
226 * @param base DMA peripheral base address.
227 * @param channel DMA channel number.
228 * @param config Pointer to the channel link configuration structure.
229 */
230 void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config);
231
232 /*!
233 * @brief Sets the DMA source address for the DMA transfer.
234 *
235 * @param base DMA peripheral base address.
236 * @param channel DMA channel number.
237 * @param srcAddr DMA source address.
238 */
DMA_SetSourceAddress(DMA_Type * base,uint32_t channel,uint32_t srcAddr)239 static inline void DMA_SetSourceAddress(DMA_Type *base, uint32_t channel, uint32_t srcAddr)
240 {
241 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
242
243 base->DMA[channel].SAR = srcAddr;
244 }
245
246 /*!
247 * @brief Sets the DMA destination address for the DMA transfer.
248 *
249 * @param base DMA peripheral base address.
250 * @param channel DMA channel number.
251 * @param destAddr DMA destination address.
252 */
DMA_SetDestinationAddress(DMA_Type * base,uint32_t channel,uint32_t destAddr)253 static inline void DMA_SetDestinationAddress(DMA_Type *base, uint32_t channel, uint32_t destAddr)
254 {
255 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
256
257 base->DMA[channel].DAR = destAddr;
258 }
259
260 /*!
261 * @brief Sets the DMA transfer size for the DMA transfer.
262 *
263 * @param base DMA peripheral base address.
264 * @param channel DMA channel number.
265 * @param size The number of bytes to be transferred.
266 */
DMA_SetTransferSize(DMA_Type * base,uint32_t channel,uint32_t size)267 static inline void DMA_SetTransferSize(DMA_Type *base, uint32_t channel, uint32_t size)
268 {
269 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
270
271 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size);
272 }
273
274 /*!
275 * @brief Sets the DMA modulo for the DMA transfer.
276 *
277 * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE)
278 * calculation is performed or the original register value. It provides the ability to implement a circular
279 * data queue easily.
280 *
281 * @param base DMA peripheral base address.
282 * @param channel DMA channel number.
283 * @param srcModulo source address modulo.
284 * @param destModulo destination address modulo.
285 */
286 void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo);
287
288 /*!
289 * @brief Enables the DMA cycle steal for the DMA transfer.
290 *
291 * If the cycle steal feature is enabled (true), the DMA controller forces a single read/write transfer per request,
292 * or it continuously makes read/write transfers until the BCR decrements to 0.
293 *
294 * @param base DMA peripheral base address.
295 * @param channel DMA channel number.
296 * @param enable The command for enable (true) or disable (false).
297 */
DMA_EnableCycleSteal(DMA_Type * base,uint32_t channel,bool enable)298 static inline void DMA_EnableCycleSteal(DMA_Type *base, uint32_t channel, bool enable)
299 {
300 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
301
302 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable);
303 }
304
305 /*!
306 * @brief Enables the DMA auto align for the DMA transfer.
307 *
308 * If the auto align feature is enabled (true), the appropriate address register increments
309 * regardless of DINC or SINC.
310 *
311 * @param base DMA peripheral base address.
312 * @param channel DMA channel number.
313 * @param enable The command for enable (true) or disable (false).
314 */
DMA_EnableAutoAlign(DMA_Type * base,uint32_t channel,bool enable)315 static inline void DMA_EnableAutoAlign(DMA_Type *base, uint32_t channel, bool enable)
316 {
317 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
318
319 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable);
320 }
321
322 /*!
323 * @brief Enables the DMA async request for the DMA transfer.
324 *
325 * If the async request feature is enabled (true), the DMA supports asynchronous DREQs
326 * while the MCU is in stop mode.
327 *
328 * @param base DMA peripheral base address.
329 * @param channel DMA channel number.
330 * @param enable The command for enable (true) or disable (false).
331 */
DMA_EnableAsyncRequest(DMA_Type * base,uint32_t channel,bool enable)332 static inline void DMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
333 {
334 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
335
336 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable);
337 }
338
339 /*!
340 * @brief Enables an interrupt for the DMA transfer.
341 *
342 * @param base DMA peripheral base address.
343 * @param channel DMA channel number.
344 */
DMA_EnableInterrupts(DMA_Type * base,uint32_t channel)345 static inline void DMA_EnableInterrupts(DMA_Type *base, uint32_t channel)
346 {
347 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
348
349 base->DMA[channel].DCR |= DMA_DCR_EINT(true);
350 }
351
352 /*!
353 * @brief Disables an interrupt for the DMA transfer.
354 *
355 * @param base DMA peripheral base address.
356 * @param channel DMA channel number.
357 */
DMA_DisableInterrupts(DMA_Type * base,uint32_t channel)358 static inline void DMA_DisableInterrupts(DMA_Type *base, uint32_t channel)
359 {
360 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
361
362 base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK;
363 }
364
365 /*! @} */
366 /*!
367 * @name DMA Channel Transfer Operation
368 * @{
369 */
370
371 /*!
372 * @brief Enables the DMA hardware channel request.
373 *
374 * @param base DMA peripheral base address.
375 * @param channel The DMA channel number.
376 */
DMA_EnableChannelRequest(DMA_Type * base,uint32_t channel)377 static inline void DMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
378 {
379 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
380
381 base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK;
382 }
383
384 /*!
385 * @brief Disables the DMA hardware channel request.
386 *
387 * @param base DMA peripheral base address.
388 * @param channel DMA channel number.
389 */
DMA_DisableChannelRequest(DMA_Type * base,uint32_t channel)390 static inline void DMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
391 {
392 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
393
394 base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK;
395 }
396
397 /*!
398 * @brief Starts the DMA transfer with a software trigger.
399 *
400 * This function starts only one read/write iteration.
401 *
402 * @param base DMA peripheral base address.
403 * @param channel The DMA channel number.
404 */
DMA_TriggerChannelStart(DMA_Type * base,uint32_t channel)405 static inline void DMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
406 {
407 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
408
409 base->DMA[channel].DCR |= DMA_DCR_START_MASK;
410 }
411
412 /*!
413 * @brief Starts the DMA enable/disable auto disable request.
414 *
415 * @param base DMA peripheral base address.
416 * @param channel The DMA channel number.
417 * @param enable true is enable, false is disable.
418 */
DMA_EnableAutoStopRequest(DMA_Type * base,uint32_t channel,bool enable)419 static inline void DMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
420 {
421 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
422
423 if (enable)
424 {
425 base->DMA[channel].DCR |= DMA_DCR_D_REQ(1);
426 }
427 else
428 {
429 base->DMA[channel].DCR &= ~DMA_DCR_D_REQ_MASK;
430 }
431 }
432
433 /*! @} */
434 /*!
435 * @name DMA Channel Status Operation
436 * @{
437 */
438
439 /*!
440 * @brief Gets the remaining bytes of the current DMA transfer.
441 *
442 * @param base DMA peripheral base address.
443 * @param channel DMA channel number.
444 * @return The number of bytes which have not been transferred yet.
445 */
DMA_GetRemainingBytes(DMA_Type * base,uint32_t channel)446 static inline uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
447 {
448 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
449
450 return (base->DMA[channel].DSR_BCR & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT;
451 }
452
453 /*!
454 * @brief Gets the DMA channel status flags.
455 *
456 * @param base DMA peripheral base address.
457 * @param channel DMA channel number.
458 * @return The mask of the channel status. Use the _dma_channel_status_flags
459 * type to decode the return 32 bit variables.
460 */
DMA_GetChannelStatusFlags(DMA_Type * base,uint32_t channel)461 static inline uint32_t DMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
462 {
463 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
464
465 return base->DMA[channel].DSR_BCR;
466 }
467
468 /*!
469 * @brief Clears the DMA channel status flags.
470 *
471 * @param base DMA peripheral base address.
472 * @param channel DMA channel number.
473 * @param mask The mask of the channel status to be cleared. Use
474 * the defined _dma_channel_status_flags type.
475 */
DMA_ClearChannelStatusFlags(DMA_Type * base,uint32_t channel,uint32_t mask)476 static inline void DMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
477 {
478 assert(channel < (uint32_t)FSL_FEATURE_DMA_MODULE_CHANNEL);
479
480 if (mask != 0U)
481 {
482 base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true);
483 }
484 }
485
486 /*! @} */
487 /*!
488 * @name DMA Channel Transactional Operation
489 * @{
490 */
491
492 /*!
493 * @brief Creates the DMA handle.
494 *
495 * This function is called first if using the transactional API for the DMA. This function
496 * initializes the internal state of the DMA handle.
497 *
498 * @param handle DMA handle pointer. The DMA handle stores callback function and
499 * parameters.
500 * @param base DMA peripheral base address.
501 * @param channel DMA channel number.
502 */
503 void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
504
505 /*!
506 * @brief Sets the DMA callback function.
507 *
508 * This callback is called in the DMA IRQ handler. Use the callback to do something
509 * after the current transfer complete.
510 *
511 * @param handle DMA handle pointer.
512 * @param callback DMA callback function pointer.
513 * @param userData Parameter for callback function. If it is not needed, just set to NULL.
514 */
515 void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
516
517 /*!
518 * @brief Prepares the DMA transfer configuration structure.
519 *
520 * This function prepares the transfer configuration structure according to the user input.
521 * The difference between this function and DMA_PrepareTransfer is that this function expose the address increment
522 * parameter to application, but in DMA_PrepareTransfer, only parts of the address increment option can be selected by
523 * dma_transfer_type_t.
524 *
525 * @param config Pointer to the user configuration structure of type dma_transfer_config_t.
526 * @param srcAddr DMA transfer source address.
527 * @param srcWidth DMA transfer source address width (byte).
528 * @param destAddr DMA transfer destination address.
529 * @param destWidth DMA transfer destination address width (byte).
530 * @param transferBytes DMA transfer bytes to be transferred.
531 * @param srcIncrement source address increment type.
532 * @param destIncrement dest address increment type.
533 */
534 void DMA_PrepareTransferConfig(dma_transfer_config_t *config,
535 void *srcAddr,
536 uint32_t srcWidth,
537 void *destAddr,
538 uint32_t destWidth,
539 uint32_t transferBytes,
540 dma_addr_increment_t srcIncrement,
541 dma_addr_increment_t destIncrement);
542
543 /*!
544 * @brief Prepares the DMA transfer configuration structure.
545 *
546 * This function prepares the transfer configuration structure according to the user input.
547 *
548 * @param config Pointer to the user configuration structure of type dma_transfer_config_t.
549 * @param srcAddr DMA transfer source address.
550 * @param srcWidth DMA transfer source address width (byte).
551 * @param destAddr DMA transfer destination address.
552 * @param destWidth DMA transfer destination address width (byte).
553 * @param transferBytes DMA transfer bytes to be transferred.
554 * @param type DMA transfer type.
555 */
556 void DMA_PrepareTransfer(dma_transfer_config_t *config,
557 void *srcAddr,
558 uint32_t srcWidth,
559 void *destAddr,
560 uint32_t destWidth,
561 uint32_t transferBytes,
562 dma_transfer_type_t type);
563
564 /*!
565 * @brief Submits the DMA transfer request.
566 *
567 * This function submits the DMA transfer request according to the transfer configuration structure.
568 *
569 * @param handle DMA handle pointer.
570 * @param config Pointer to DMA transfer configuration structure.
571 * @param options Additional configurations for transfer. Use
572 * the defined dma_transfer_options_t type.
573 * @retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded.
574 * @retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed.
575 * @note This function can't process multi transfer request.
576 */
577 status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options);
578
579 /*!
580 * @brief DMA starts a transfer.
581 *
582 * This function enables the channel request. Call this function
583 * after submitting a transfer request.
584 *
585 * @param handle DMA handle pointer.
586 * @retval kStatus_DMA_Success It indicates that the DMA start transfer succeed.
587 * @retval kStatus_DMA_Busy It indicates that the DMA has started a transfer.
588 */
DMA_StartTransfer(dma_handle_t * handle)589 static inline void DMA_StartTransfer(dma_handle_t *handle)
590 {
591 assert(handle != NULL);
592
593 handle->base->DMA[handle->channel].DCR |= DMA_DCR_ERQ_MASK;
594 }
595
596 /*!
597 * @brief DMA stops a transfer.
598 *
599 * This function disables the channel request to stop a DMA transfer.
600 * The transfer can be resumed by calling the DMA_StartTransfer.
601 *
602 * @param handle DMA handle pointer.
603 */
DMA_StopTransfer(dma_handle_t * handle)604 static inline void DMA_StopTransfer(dma_handle_t *handle)
605 {
606 assert(handle != NULL);
607
608 handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK;
609 }
610
611 /*!
612 * @brief DMA aborts a transfer.
613 *
614 * This function disables the channel request and clears all status bits.
615 * Submit another transfer after calling this API.
616 *
617 * @param handle DMA handle pointer.
618 */
619 void DMA_AbortTransfer(dma_handle_t *handle);
620
621 /*!
622 * @brief DMA IRQ handler for current transfer complete.
623 *
624 * This function clears the channel interrupt flag and calls
625 * the callback function if it is not NULL.
626 *
627 * @param handle DMA handle pointer.
628 */
629 void DMA_HandleIRQ(dma_handle_t *handle);
630
631 /*! @} */
632
633 #if defined(__cplusplus)
634 }
635 #endif /* __cplusplus */
636
637 /*! @} */
638
639 #endif /* FSL_DMA_H_ */
640
