1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_CTIMER_H_
9 #define FSL_CTIMER_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup ctimer
15 * @{
16 */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*! @{ */
26 #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
27 /*! @} */
28
29 /*! @brief List of Timer capture channels */
30 typedef enum _ctimer_capture_channel
31 {
32 kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
33 kCTIMER_Capture_1, /*!< Timer capture channel 1 */
34 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
35 kCTIMER_Capture_2, /*!< Timer capture channel 2 */
36 #endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
37 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
38 kCTIMER_Capture_3 /*!< Timer capture channel 3 */
39 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
40 } ctimer_capture_channel_t;
41
42 /*! @brief List of capture edge options */
43 typedef enum _ctimer_capture_edge
44 {
45 kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
46 kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
47 kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
48 } ctimer_capture_edge_t;
49
50 /*! @brief List of Timer match registers */
51 typedef enum _ctimer_match
52 {
53 kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
54 kCTIMER_Match_1, /*!< Timer match register 1 */
55 kCTIMER_Match_2, /*!< Timer match register 2 */
56 kCTIMER_Match_3 /*!< Timer match register 3 */
57 } ctimer_match_t;
58
59 /*! @brief List of external match */
60 typedef enum _ctimer_external_match
61 {
62 kCTIMER_External_Match_0 = (1UL << 0), /*!< External match 0 */
63 kCTIMER_External_Match_1 = (1UL << 1), /*!< External match 1 */
64 kCTIMER_External_Match_2 = (1UL << 2), /*!< External match 2 */
65 kCTIMER_External_Match_3 = (1UL << 3) /*!< External match 3 */
66 } ctimer_external_match_t;
67
68 /*! @brief List of output control options */
69 typedef enum _ctimer_match_output_control
70 {
71 kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
72 kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */
73 kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */
74 kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */
75 } ctimer_match_output_control_t;
76
77 /*! @brief List of Timer modes */
78 typedef enum _ctimer_timer_mode
79 {
80 kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */
81 kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
82 kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
83 kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */
84 } ctimer_timer_mode_t;
85
86 /*! @brief List of Timer interrupts */
87 typedef enum _ctimer_interrupt_enable
88 {
89 kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
90 kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */
91 kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */
92 kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */
93 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
94 kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
95 kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
96 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
97 kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
98 #endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
99 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
100 kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
101 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
102 #endif
103 } ctimer_interrupt_enable_t;
104
105 /*! @brief List of Timer flags */
106 typedef enum _ctimer_status_flags
107 {
108 kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */
109 kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */
110 kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */
111 kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */
112 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
113 kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
114 kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
115 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT)
116 kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
117 #endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */
118 #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
119 kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
120 #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
121 #endif
122 } ctimer_status_flags_t;
123
124 typedef void (*ctimer_callback_t)(uint32_t flags);
125
126 /*! @brief Callback type when registering for a callback. When registering a callback
127 * an array of function pointers is passed the size could be 1 or 8, the callback
128 * type will tell that.
129 */
130 typedef enum
131 {
132 kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
133 based on the status flags different channels needs to be handled differently */
134 kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
135 for both match/capture */
136 } ctimer_callback_type_t;
137
138 /*!
139 * @brief Match configuration
140 *
141 * This structure holds the configuration settings for each match register.
142 */
143 typedef struct _ctimer_match_config
144 {
145 uint32_t matchValue; /*!< This is stored in the match register */
146 bool enableCounterReset; /*!< true: Match will reset the counter
147 false: Match will not reser the counter */
148 bool enableCounterStop; /*!< true: Match will stop the counter
149 false: Match will not stop the counter */
150 ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
151 bool outPinInitState; /*!< Initial value of the EM bit/output */
152 bool enableInterrupt; /*!< true: Generate interrupt upon match
153 false: Do not generate interrupt on match */
154
155 } ctimer_match_config_t;
156
157 /*!
158 * @brief Timer configuration structure
159 *
160 * This structure holds the configuration settings for the Timer peripheral. To initialize this
161 * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
162 * pointer to the configuration structure instance.
163 *
164 * The configuration structure can be made constant so as to reside in flash.
165 */
166 typedef struct _ctimer_config
167 {
168 ctimer_timer_mode_t mode; /*!< Timer mode */
169 ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
170 modes that rely on this input signal to increment TC */
171 uint32_t prescale; /*!< Prescale value */
172 } ctimer_config_t;
173
174 /*******************************************************************************
175 * API
176 ******************************************************************************/
177
178 #if defined(__cplusplus)
179 extern "C" {
180 #endif
181
182 /*!
183 * @name Initialization and deinitialization
184 * @{
185 */
186
187 /*!
188 * @brief Ungates the clock and configures the peripheral for basic operation.
189 *
190 * @note This API should be called at the beginning of the application before using the driver.
191 *
192 * @param base Ctimer peripheral base address
193 * @param config Pointer to the user configuration structure.
194 */
195 void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
196
197 /*!
198 * @brief Gates the timer clock.
199 *
200 * @param base Ctimer peripheral base address
201 */
202 void CTIMER_Deinit(CTIMER_Type *base);
203
204 /*!
205 * @brief Fills in the timers configuration structure with the default settings.
206 *
207 * The default values are:
208 * @code
209 * config->mode = kCTIMER_TimerMode;
210 * config->input = kCTIMER_Capture_0;
211 * config->prescale = 0;
212 * @endcode
213 * @param config Pointer to the user configuration structure.
214 */
215 void CTIMER_GetDefaultConfig(ctimer_config_t *config);
216
217 /*! @}*/
218
219 /*!
220 * @name PWM setup operations
221 * @{
222 */
223
224 /*!
225 * @brief Configures the PWM signal parameters.
226 *
227 * Enables PWM mode on the match channel passed in and will then setup the match value
228 * and other match parameters to generate a PWM signal.
229 * This function can manually assign the specified channel to set the PWM cycle.
230 *
231 * @note When setting PWM output from multiple output pins, all should use the same PWM
232 * period
233 *
234 * @param base Ctimer peripheral base address
235 * @param pwmPeriodChannel Specify the channel to control the PWM period
236 * @param matchChannel Match pin to be used to output the PWM signal
237 * @param pwmPeriod PWM period match value
238 * @param pulsePeriod Pulse width match value
239 * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
240 * if it is 0 then no interrupt will be generated.
241 */
242 status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
243 const ctimer_match_t pwmPeriodChannel,
244 ctimer_match_t matchChannel,
245 uint32_t pwmPeriod,
246 uint32_t pulsePeriod,
247 bool enableInt);
248
249 /*!
250 * @brief Configures the PWM signal parameters.
251 *
252 * Enables PWM mode on the match channel passed in and will then setup the match value
253 * and other match parameters to generate a PWM signal.
254 * This function can manually assign the specified channel to set the PWM cycle.
255 *
256 * @note When setting PWM output from multiple output pins, all should use the same PWM
257 * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
258 *
259 * @param base Ctimer peripheral base address
260 * @param pwmPeriodChannel Specify the channel to control the PWM period
261 * @param matchChannel Match pin to be used to output the PWM signal
262 * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
263 * @param pwmFreq_Hz PWM signal frequency in Hz
264 * @param srcClock_Hz Timer counter clock in Hz
265 * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
266 * if it is 0 then no interrupt will be generated.
267 */
268 status_t CTIMER_SetupPwm(CTIMER_Type *base,
269 const ctimer_match_t pwmPeriodChannel,
270 ctimer_match_t matchChannel,
271 uint8_t dutyCyclePercent,
272 uint32_t pwmFreq_Hz,
273 uint32_t srcClock_Hz,
274 bool enableInt);
275
276 /*!
277 * @brief Updates the pulse period of an active PWM signal.
278 *
279 * @param base Ctimer peripheral base address
280 * @param matchChannel Match pin to be used to output the PWM signal
281 * @param pulsePeriod New PWM pulse width match value
282 */
CTIMER_UpdatePwmPulsePeriod(CTIMER_Type * base,ctimer_match_t matchChannel,uint32_t pulsePeriod)283 static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)
284 {
285 /* Update PWM pulse period match value */
286 base->MR[matchChannel] = pulsePeriod;
287 }
288
289 /*!
290 * @brief Updates the duty cycle of an active PWM signal.
291 *
292 * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution.
293 * This function can manually assign the specified channel to set the PWM cycle.
294 *
295 * @param base Ctimer peripheral base address
296 * @param pwmPeriodChannel Specify the channel to control the PWM period
297 * @param matchChannel Match pin to be used to output the PWM signal
298 * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
299 */
300 void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base,
301 const ctimer_match_t pwmPeriodChannel,
302 ctimer_match_t matchChannel,
303 uint8_t dutyCyclePercent);
304
305 /*! @}*/
306
307 /*!
308 * @brief Setup the match register.
309 *
310 * User configuration is used to setup the match value and action to be taken when a match occurs.
311 *
312 * @param base Ctimer peripheral base address
313 * @param matchChannel Match register to configure
314 * @param config Pointer to the match configuration structure
315 */
316 void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
317
318 /*!
319 * @brief Get the status of output match.
320 *
321 * This function gets the status of output MAT, whether or not this output is connected to a pin.
322 * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
323 *
324 * @param base Ctimer peripheral base address
325 * @param matchChannel External match channel, user can obtain the status of multiple match channels
326 * at the same time by using the logic of "|"
327 * enumeration ::ctimer_external_match_t
328 * @return The mask of external match channel status flags. Users need to use the
329 * _ctimer_external_match type to decode the return variables.
330 */
331 uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel);
332
333 /*!
334 * @brief Setup the capture.
335 *
336 * @param base Ctimer peripheral base address
337 * @param capture Capture channel to configure
338 * @param edge Edge on the channel that will trigger a capture
339 * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
340 * is called upon capture
341 */
342 void CTIMER_SetupCapture(CTIMER_Type *base,
343 ctimer_capture_channel_t capture,
344 ctimer_capture_edge_t edge,
345 bool enableInt);
346
347 /*!
348 * @brief Get the timer count value from TC register.
349 *
350 * @param base Ctimer peripheral base address.
351 * @return return the timer count value.
352 */
CTIMER_GetTimerCountValue(CTIMER_Type * base)353 static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)
354 {
355 return (base->TC);
356 }
357
358 /*!
359 * @brief Register callback.
360 *
361 * @param base Ctimer peripheral base address
362 * @param cb_func callback function
363 * @param cb_type callback function type, singular or multiple
364 */
365 void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
366
367 /*!
368 * @name Interrupt Interface
369 * @{
370 */
371
372 /*!
373 * @brief Enables the selected Timer interrupts.
374 *
375 * @param base Ctimer peripheral base address
376 * @param mask The interrupts to enable. This is a logical OR of members of the
377 * enumeration ::ctimer_interrupt_enable_t
378 */
CTIMER_EnableInterrupts(CTIMER_Type * base,uint32_t mask)379 static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
380 {
381 /* Enable match interrupts */
382 base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
383
384 /* Enable capture interrupts */
385 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
386 base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
387 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
388 | CTIMER_CCR_CAP2I_MASK
389 #endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
390 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
391 | CTIMER_CCR_CAP3I_MASK
392 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
393 );
394 #endif
395 }
396
397 /*!
398 * @brief Disables the selected Timer interrupts.
399 *
400 * @param base Ctimer peripheral base address
401 * @param mask The interrupts to enable. This is a logical OR of members of the
402 * enumeration ::ctimer_interrupt_enable_t
403 */
CTIMER_DisableInterrupts(CTIMER_Type * base,uint32_t mask)404 static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
405 {
406 /* Disable match interrupts */
407 base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
408
409 /* Disable capture interrupts */
410 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
411 base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
412 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
413 | CTIMER_CCR_CAP2I_MASK
414 #endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
415 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
416 | CTIMER_CCR_CAP3I_MASK
417 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
418 ));
419 #endif
420 }
421
422 /*!
423 * @brief Gets the enabled Timer interrupts.
424 *
425 * @param base Ctimer peripheral base address
426 *
427 * @return The enabled interrupts. This is the logical OR of members of the
428 * enumeration ::ctimer_interrupt_enable_t
429 */
CTIMER_GetEnabledInterrupts(CTIMER_Type * base)430 static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
431 {
432 uint32_t enabledIntrs = 0;
433
434 /* Get all the match interrupts enabled */
435 enabledIntrs =
436 base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
437
438 /* Get all the capture interrupts enabled */
439 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
440 enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
441 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
442 | CTIMER_CCR_CAP2I_MASK
443 #endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
444 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
445 | CTIMER_CCR_CAP3I_MASK
446 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
447 );
448 #endif
449
450 return enabledIntrs;
451 }
452
453 /*! @}*/
454
455 /*!
456 * @name Status Interface
457 * @{
458 */
459
460 /*!
461 * @brief Gets the Timer status flags.
462 *
463 * @param base Ctimer peripheral base address
464 *
465 * @return The status flags. This is the logical OR of members of the
466 * enumeration ::ctimer_status_flags_t
467 */
CTIMER_GetStatusFlags(CTIMER_Type * base)468 static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
469 {
470 return base->IR;
471 }
472
473 /*!
474 * @brief Clears the Timer status flags.
475 *
476 * @param base Ctimer peripheral base address
477 * @param mask The status flags to clear. This is a logical OR of members of the
478 * enumeration ::ctimer_status_flags_t
479 */
CTIMER_ClearStatusFlags(CTIMER_Type * base,uint32_t mask)480 static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
481 {
482 base->IR = mask;
483 }
484
485 /*! @}*/
486
487 /*!
488 * @name Counter Start and Stop
489 * @{
490 */
491
492 /*!
493 * @brief Starts the Timer counter.
494 *
495 * @param base Ctimer peripheral base address
496 */
CTIMER_StartTimer(CTIMER_Type * base)497 static inline void CTIMER_StartTimer(CTIMER_Type *base)
498 {
499 base->TCR |= CTIMER_TCR_CEN_MASK;
500 }
501
502 /*!
503 * @brief Stops the Timer counter.
504 *
505 * @param base Ctimer peripheral base address
506 */
CTIMER_StopTimer(CTIMER_Type * base)507 static inline void CTIMER_StopTimer(CTIMER_Type *base)
508 {
509 base->TCR &= ~CTIMER_TCR_CEN_MASK;
510 }
511
512 /*! @}*/
513
514 /*!
515 * @brief Reset the counter.
516 *
517 * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
518 *
519 * @param base Ctimer peripheral base address
520 */
CTIMER_Reset(CTIMER_Type * base)521 static inline void CTIMER_Reset(CTIMER_Type *base)
522 {
523 base->TCR |= CTIMER_TCR_CRST_MASK;
524 base->TCR &= ~CTIMER_TCR_CRST_MASK;
525 }
526
527 /*!
528 * @brief Setup the timer prescale value.
529 *
530 * Specifies the maximum value for the Prescale Counter.
531 *
532 * @param base Ctimer peripheral base address
533 * @param prescale Prescale value
534 */
CTIMER_SetPrescale(CTIMER_Type * base,uint32_t prescale)535 static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale)
536 {
537 base->PR = CTIMER_PR_PRVAL(prescale);
538 }
539
540 /*!
541 * @brief Get capture channel value.
542 *
543 * Get the counter/timer value on the corresponding capture channel.
544 *
545 * @param base Ctimer peripheral base address
546 * @param capture Select capture channel
547 *
548 * @return The timer count capture value.
549 */
CTIMER_GetCaptureValue(CTIMER_Type * base,ctimer_capture_channel_t capture)550 static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture)
551 {
552 return base->CR[capture];
553 }
554
555 /*!
556 * @brief Enable reset match channel.
557 *
558 * Set the specified match channel reset operation.
559 *
560 * @param base Ctimer peripheral base address
561 * @param match match channel used
562 * @param enable Enable match channel reset operation.
563 */
CTIMER_EnableResetMatchChannel(CTIMER_Type * base,ctimer_match_t match,bool enable)564 static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)
565 {
566 if (enable)
567 {
568 base->MCR |= (1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U)));
569 }
570 else
571 {
572 base->MCR &= ~(1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U)));
573 }
574 }
575
576 /*!
577 * @brief Enable stop match channel.
578 *
579 * Set the specified match channel stop operation.
580 *
581 * @param base Ctimer peripheral base address.
582 * @param match match channel used.
583 * @param enable Enable match channel stop operation.
584 */
CTIMER_EnableStopMatchChannel(CTIMER_Type * base,ctimer_match_t match,bool enable)585 static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)
586 {
587 if (enable)
588 {
589 base->MCR |= (1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U)));
590 }
591 else
592 {
593 base->MCR &= ~(1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U)));
594 }
595 }
596
597 #if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR))
598 /*!
599 * @brief Enable reload channel falling edge.
600 *
601 * Enable the specified match channel reload match shadow value.
602 *
603 * @param base Ctimer peripheral base address.
604 * @param match match channel used.
605 * @param enable Enable .
606 */
CTIMER_EnableMatchChannelReload(CTIMER_Type * base,ctimer_match_t match,bool enable)607 static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable)
608 {
609 if (enable)
610 {
611 base->MCR |= (1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match));
612 }
613 else
614 {
615 base->MCR &= ~(1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match));
616 }
617 }
618 #endif /* FSL_FEATURE_CTIMER_HAS_MSR */
619
620 /*!
621 * @brief Enable capture channel rising edge.
622 *
623 * Sets the specified capture channel for rising edge capture.
624 *
625 * @param base Ctimer peripheral base address.
626 * @param capture capture channel used.
627 * @param enable Enable rising edge capture.
628 */
CTIMER_EnableRisingEdgeCapture(CTIMER_Type * base,ctimer_capture_channel_t capture,bool enable)629 static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)
630 {
631 if (enable)
632 {
633 base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)));
634 }
635 else
636 {
637 base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)));
638 }
639 }
640
641 /*!
642 * @brief Enable capture channel falling edge.
643 *
644 * Sets the specified capture channel for falling edge capture.
645 *
646 * @param base Ctimer peripheral base address.
647 * @param capture capture channel used.
648 * @param enable Enable falling edge capture.
649 */
CTIMER_EnableFallingEdgeCapture(CTIMER_Type * base,ctimer_capture_channel_t capture,bool enable)650 static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)
651 {
652 if (enable)
653 {
654 base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U)));
655 }
656 else
657 {
658 base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U)));
659 }
660 }
661
662 #if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR))
663 /*!
664 * @brief Set the specified match shadow channel.
665 *
666 * @param base Ctimer peripheral base address.
667 * @param match match channel used.
668 * @param matchvalue Reload the value of the corresponding match register.
669 */
CTIMER_SetShadowValue(CTIMER_Type * base,ctimer_match_t match,uint32_t matchvalue)670 static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue)
671 {
672 base->MSR[match] = matchvalue;
673 }
674 #endif /* FSL_FEATURE_CTIMER_HAS_MSR */
675
676 #if defined(__cplusplus)
677 }
678 #endif
679
680 /*! @}*/
681
682 #endif /* FSL_CTIMER_H_ */
683
