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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_sc_event.c219 uint8_t group = (uint8_t)SC_EVENT_GET_IRQ_GROUP(event); in SCEvent_Config() local
225 if ((s_irqEnabled[group] == 0U) && enable) in SCEvent_Config()
227 err = sc_irq_status(ipc, IPC_MU_RSRC, group, &status); in SCEvent_Config()
236 err = sc_irq_enable(ipc, IPC_MU_RSRC, group, (0x1UL << pt), enable); in SCEvent_Config()
244 s_irqEnabled[group] |= 0x1UL << pt; in SCEvent_Config()
249 s_irqEnabled[group] &= (~(0x1UL << pt)) & SC_EVENT_IRQ_DUMMY; in SCEvent_Config()
254 err = sc_irq_enable(ipc, IPC_MU_RSRC, group, mask, enable); in SCEvent_Config()
261 s_irqEnabled[group] |= mask; in SCEvent_Config()
265 s_irqEnabled[group] &= ~mask; in SCEvent_Config()
316 uint8_t group; /* Event group. */ in SCEvent_Process() local
[all …]
/hal_nxp-3.7.0/mcux/scripts/pinctrl/imx/
Dimx_fixup_pinmux.py52 mux_reg = int(match.group(2), 0)
53 mux = int(match.group(3), 0)
54 daisy_reg = int(match.group(4), 0)
55 daisy = int(match.group(5), 0)
56 cfg_reg = int(match.group(6), 0)
59 ground_truth[(mux_reg, mux)] = (match.group(1), daisy_reg, daisy, cfg_reg)
81 mux_reg = int(match2.group(1), 0)
82 mux = int(match2.group(2), 0)
83 daisy_reg = int(match2.group(3), 0)
84 daisy = int(match2.group(4), 0)
[all …]
Dimx_cfg_utils.py237 periph_name = match.group(1)
242 reg_name = match.group(1)
244 pad_name = match.group(1)
412 gpio_port = match.group(1)
421 periph_name = match.group(1)
423 reg_name = match.group(1)
882 self._soc = re.match(r'MIMXR?T?[0-9]+(M\w\d)*', self._soc_sku).group(0)
966 if opt_match.group(1):
967 pin = int(opt_match.group(1))
968 elif opt_match.group(2):
[all …]
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/sdu/
Dfsl_sdioslv_sdu.c23 sdioslv_scratch_group_t group,
359 sdioslv_scratch_group_t group, in SDIOSLV_ReadScratchRegister() argument
366 ret = SDIOSLV_GetScratchRegisterAddr(fun_num, group, offset, &reg_addr); in SDIOSLV_ReadScratchRegister()
387 sdioslv_scratch_group_t group, in SDIOSLV_WriteScratchRegister() argument
394 ret = SDIOSLV_GetScratchRegisterAddr(fun_num, group, offset, &reg_addr); in SDIOSLV_WriteScratchRegister()
417 sdioslv_scratch_group_t group, in SDIOSLV_GetScratchRegisterAddr() argument
421 switch (group) in SDIOSLV_GetScratchRegisterAddr()
445 *reg_addr = SDU_SCRATCH2_OFFSET0_ADDR + (group - 2) * 4 + offset; in SDIOSLV_GetScratchRegisterAddr()
/hal_nxp-3.7.0/mcux/scripts/pinctrl/kinetis/
Dkinetis_cfg_utils.py67 self._port = match.group(1)
68 self._pin = int(match.group(2))
176 self._port = pin_regex.group(1)
177 self._pin = pin_regex.group(2)
603 group = PinGroup(function, self._pins)
604 pin_groups[group.get_name()] = group
630 for group in pin_groups.values():
631 pin_props = group.get_pin_props()
635 logging.info("Writing pin group %s to disk", group.get_name())
637 description = group.get_description()
[all …]
/hal_nxp-3.7.0/mcux/scripts/pinctrl/lpc/
Dlpc_cfg_utils.py64 port = int(match.group(1))
65 pin = int(match.group(2))
226 self._port = int(pin_regex.group(1))
227 self._pin = int(pin_regex.group(2))
721 group = PinGroup(function, self._pins, self._imx_rt)
722 pin_groups[group.get_name()] = group
752 for group in pin_groups.values():
753 pin_props = group.get_pin_props()
754 description = group.get_description()
765 logging.info("Writing pin group %s to disk", group.get_name())
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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/dpu/
Dfsl_dpu.c1255 void DPU_EnableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask) in DPU_EnableInterrupts() argument
1257 assert(group < DPU_INT_GROUP_NUM); in DPU_EnableInterrupts()
1259 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTENABLE[group] |= mask; in DPU_EnableInterrupts()
1280 void DPU_DisableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask) in DPU_DisableInterrupts() argument
1282 assert(group < DPU_INT_GROUP_NUM); in DPU_DisableInterrupts()
1284 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTENABLE[group] &= ~mask; in DPU_DisableInterrupts()
1296 uint32_t DPU_GetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group) in DPU_GetInterruptsPendingFlags() argument
1298 assert(group < DPU_INT_GROUP_NUM); in DPU_GetInterruptsPendingFlags()
1300 return ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTSTATUS[group]; in DPU_GetInterruptsPendingFlags()
1321 void DPU_ClearInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask) in DPU_ClearInterruptsPendingFlags() argument
[all …]
Dfsl_dpu.h871 void DPU_EnableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
891 void DPU_DisableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
916 uint32_t DPU_GetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group);
936 void DPU_ClearInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
951 void DPU_SetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
965 void DPU_MaskUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
978 void DPU_EnableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
991 void DPU_DisableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
1003 uint32_t DPU_GetUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group);
1016 void DPU_ClearUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask);
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
Dirq_api.h175 sc_irq_group_t group, uint32_t mask, sc_bool_t enable);
195 sc_irq_group_t group, uint32_t *status);
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
Dirq_api.h175 sc_irq_group_t group, uint32_t mask, sc_bool_t enable);
195 sc_irq_group_t group, uint32_t *status);
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/svc/irq/
Dirq_rpc_clnt.c55 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_enable() argument
68 RPC_U8(&msg, 6U) = U8(group); in sc_irq_enable()
78 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, in sc_irq_status() argument
90 RPC_U8(&msg, 2U) = U8(group); in sc_irq_status()

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