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Searched refs:TBCT (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.c164 base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK; in QSPI_Init()
165 base->TBCT |= QuadSPI_TBCT_WMRK((uint32_t)config->txWatermark - 1U); in QSPI_Init()
Dfsl_qspi_edma.c152 handle->count = (uint8_t)base->TBCT + 1U; in QSPI_TransferTxCreateHandleEDMA()
/hal_nxp-3.7.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h872 uint32 RegValue = (uint32)BaseAddr->TBCT; in Qspi_Ip_SetTxWatermark()
876 BaseAddr->TBCT = (uint32)RegValue; in Qspi_Ip_SetTxWatermark()
/hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h100 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h106 __IO uint32_t TBCT; /**< TX Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c2043 BaseAddr->TBCT = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h116 __IO uint32_t TBCT; /**< TX Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18278 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19251 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17780 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17782 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25121 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25122 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ member