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Searched refs:SW_MUX_CTL_PAD_SD3_DATA1 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15780 __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA1; /**< Pad Mux Register, offset: 0x25C */ member
16329 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1)
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h21760 …__IO uint32_t SW_MUX_CTL_PAD_SD3_DATA1; /**< SW_MUX_CTL_PAD_SD3_DATA1 SW MUX Contro… member
22231 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1)