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Searched refs:SW_MUX_CTL_PAD_GPIO1_IO09 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15643 __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO09; /**< Pad Mux Register, offset: 0x38 */ member
16192 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09)
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h21647 …__IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO09; /**< SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Contr… member
22118 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09)