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Searched refs:SIM_PLATCGC_CGCEIM_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/
DS32K118_SIM.h349 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
352 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K116_SIM.h349 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
352 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K144_SIM.h425 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
428 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K142W_SIM.h445 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
448 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K142_SIM.h425 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
428 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K144W_SIM.h445 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
448 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K146_SIM.h470 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
473 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
DS32K148_SIM.h505 #define SIM_PLATCGC_CGCEIM_MASK (0x10U) macro
508 … (((uint32_t)(((uint32_t)(x)) << SIM_PLATCGC_CGCEIM_SHIFT)) & SIM_PLATCGC_CGCEIM_MASK)
/hal_nxp-3.7.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Frequency.c1023 …Frequency &= Clock_Ip_u32EnableGate[((IP_SIM->PLATCGC & SIM_PLATCGC_CGCEIM_MASK) >> SIM_PLATCGC_CG… in get_EIM0_CLK_Frequency()