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Searched refs:SAR (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/dma/
Dfsl_dma.c114 base->DMA[channel].SAR = 0; in DMA_ResetChannel()
153 base->DMA[channel].SAR = config->srcAddr; in DMA_SetTransferConfig()
Dfsl_dma.h243 base->DMA[channel].SAR = srcAddr; in DMA_SetSourceAddress()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h857 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h1280 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h1289 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h1614 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h1614 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h1614 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h3702 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h1250 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h1250 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h1250 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h3700 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h3704 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h4057 …__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h4148 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ member
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h11442 } SAR[4]; member
11466 #define DDRC_MP_SARBASE_REG(base,index) ((base)->SAR[index].SARBASE)
11467 #define DDRC_MP_SARSIZE_REG(base,index) ((base)->SAR[index].SARSIZE)