| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z7/ |
| D | MKV10Z7.h | 9030 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV30F12810/ |
| D | MKV30F12810.h | 9122 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK02F12810/ |
| D | MK02F12810.h | 9089 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F12810/ |
| D | MKV31F12810.h | 9908 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z1287/ |
| D | MKV10Z1287.h | 10066 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW40Z4/ |
| D | MKW40Z4.h | 7372 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
7404 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW30Z4/ |
| D | MKW30Z4.h | 7372 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
7404 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW20Z4/ |
| D | MKW20Z4.h | 7372 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
7404 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV11Z7/ |
| D | MKV11Z7.h | 10854 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F51212/ |
| D | MKV31F51212.h | 11367 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F25612/ |
| D | MKV31F25612.h | 10979 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F12810/ |
| D | MK22F12810.h | 11174 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW24D5/ |
| D | MKW24D5.h | 6880 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW22D5/ |
| D | MKW22D5.h | 6880 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F25612/ |
| D | MK22F25612.h | 12294 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F51212/ |
| D | MK22F51212.h | 12692 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F12/ |
| D | MK22F12.h | 16961 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW31Z4/ |
| D | MKW31Z4.h | 6702 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK24F12/ |
| D | MK24F12.h | 20582 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK63F12/ |
| D | MK63F12.h | 22393 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK64F12/ |
| D | MK64F12.h | 22439 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW41Z4/ |
| D | MKW41Z4.h | 6702 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW21Z4/ |
| D | MKW21Z4.h | 6631 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV56F24/ |
| D | MKV56F24.h | 24047 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV58F24/ |
| D | MKV58F24.h | 25813 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ member
|
