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Searched refs:QuadSPI_FR_ABSEF_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h604 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
607 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h111 kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18892 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
18894 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19865 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
19867 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18422 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
18424 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18424 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
18426 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25571 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
25573 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25572 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
25574 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44427 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
44429 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46600 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
46602 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46600 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
46602 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46600 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
46602 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46600 #define QuadSPI_FR_ABSEF_MASK (0x8000U) macro
46602 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30691 #define QuadSPI_FR_ABSEF_MASK 0x8000u macro
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37890 #define QuadSPI_FR_ABSEF_MASK 0x8000u macro