PLL_PLLODIV_DE_SHIFT (reference) in projects: hal_nxp-3.7.0

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Searched refs:PLL_PLLODIV_DE_SHIFT (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/
D	S32K344_PLL.h	`217 #define PLL_PLLODIV_DE_SHIFT (31U) macro 219 …ODIV_DE(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLLODIV_DE_SHIFT)) & PLL_PLL…`
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Frequency.c	1850 …au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; … in Clock_Ip_Get_PLL_PHI0_Frequency() 1857 …au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; … in Clock_Ip_Get_PLL_PHI1_Frequency() 1865 …EnableDivider[((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; … in Clock_Ip_Get_PLLAUX_PHI0_Frequency() 1874 …EnableDivider[((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; … in Clock_Ip_Get_PLLAUX_PHI1_Frequency() 1883 …EnableDivider[((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; … in Clock_Ip_Get_PLLAUX_PHI2_Frequency()

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
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