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Searched refs:PLL_PLLCR_PLLPD_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Pll.c176 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
220 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
241 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLL_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
278 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
313 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
340 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_SetPllRdivMfiMfnOdiv2Sdmen()
361 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLL_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePllRdivMfiMfnOdiv2Sdmen()
397 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePllRdivMfiMfnOdiv2Sdmen()
/hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_PLL.h112 #define PLL_PLLCR_PLLPD_MASK (0x80000000U) macro
115 … (((uint32_t)(((uint32_t)(x)) << PLL_PLLCR_PLLPD_SHIFT)) & PLL_PLLCR_PLLPD_MASK)