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Searched refs:MUX_DIV_TRIG_CTRL (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_DividerTrigger.c138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
DClock_Ip_Divider.c269 …if ((Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_M… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_DividerTrigger.c138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h212 uint32 MUX_DIV_TRIG_CTRL; /**< Clock Divider trigger Control Register */ member
/hal_nxp-3.7.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h366 …uint32 MUX_DIV_TRIG_CTRL; /**< Clock Mux 0 Divider Trigger Control Register, offset:… member