| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/cmp/ |
| D | fsl_cmp.h | 249 base->MUXCR |= CMP_MUXCR_PSTM_MASK; in CMP_EnablePassThroughMode()
253 base->MUXCR &= (uint8_t)(~CMP_MUXCR_PSTM_MASK); in CMP_EnablePassThroughMode()
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| D | fsl_cmp.c | 192 uint8_t tmp8 = base->MUXCR; in CMP_SetInputChannels()
196 base->MUXCR = tmp8; in CMP_SetInputChannels()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL25Z4/ |
| D | MKL25Z4.h | 608 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL17Z644/ |
| D | MKL17Z644.h | 767 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKL27Z644/ |
| D | MKL27Z644.h | 776 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z7/ |
| D | MKV10Z7.h | 753 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV30F12810/ |
| D | MKV30F12810.h | 839 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK02F12810/ |
| D | MK02F12810.h | 835 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F12810/ |
| D | MKV31F12810.h | 852 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV10Z1287/ |
| D | MKV10Z1287.h | 744 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW40Z4/ |
| D | MKW40Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW30Z4/ |
| D | MKW30Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW20Z4/ |
| D | MKW20Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKM14ZA5/ |
| D | MKM14ZA5.h | 3100 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV11Z7/ |
| D | MKV11Z7.h | 1531 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F51212/ |
| D | MKV31F51212.h | 854 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKV31F25612/ |
| D | MKV31F25612.h | 854 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B31A/ |
| D | K32L2B31A.h | 792 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F12810/ |
| D | MK22F12810.h | 854 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B21A/ |
| D | K32L2B21A.h | 792 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2B11A/ |
| D | K32L2B11A.h | 792 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW24D5/ |
| D | MKW24D5.h | 1159 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MKW22D5/ |
| D | MKW22D5.h | 1159 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F25612/ |
| D | MK22F25612.h | 860 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK22F51212/ |
| D | MK22F51212.h | 870 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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