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Searched refs:MPWLDECTRL0 (Results 1 – 1 of 1) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h26165 …__IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control … member
26256 #define MMDC_MPWLDECTRL0_REG(base) ((base)->MPWLDECTRL0)