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Searched refs:MPDGCTRL0 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h26177 …__IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Regis… member
26268 #define MMDC_MPDGCTRL0_REG(base) ((base)->MPDGCTRL0)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h16913 …__IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0,… member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h16914 …__IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0,… member