1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MC_ME.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MC_ME 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MC_ME_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MC_ME_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_ME Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_ME_Peripheral_Access_Layer MC_ME Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_ME - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CTL_KEY; /**< Control Key Register, offset: 0x0 */ 74 __IO uint32_t MODE_CONF; /**< Mode Configuration Register, offset: 0x4 */ 75 __IO uint32_t MODE_UPD; /**< Mode Update Register, offset: 0x8 */ 76 __I uint32_t MODE_STAT; /**< Mode Status Register, offset: 0xC */ 77 __IO uint32_t MAIN_COREID; /**< Main Core ID Register, offset: 0x10 */ 78 uint8_t RESERVED_0[236]; 79 __IO uint32_t PRTN0_PCONF; /**< Partition 0 Process Configuration Register, offset: 0x100 */ 80 __IO uint32_t PRTN0_PUPD; /**< Partition 0 Process Update Register, offset: 0x104 */ 81 __I uint32_t PRTN0_STAT; /**< Partition 0 Status Register, offset: 0x108 */ 82 uint8_t RESERVED_1[8]; 83 __I uint32_t PRTN0_COFB1_STAT; /**< Partition 0 COFB Set 1 Clock Status Register, offset: 0x114 */ 84 uint8_t RESERVED_2[28]; 85 __IO uint32_t PRTN0_COFB1_CLKEN; /**< Partition 0 COFB Set 1 Clock Enable Register, offset: 0x134 */ 86 uint8_t RESERVED_3[8]; 87 __IO uint32_t PRTN0_CORE0_PCONF; /**< Partition 0 Core 0 Process Configuration Register, offset: 0x140 */ 88 __IO uint32_t PRTN0_CORE0_PUPD; /**< Partition 0 Core 0 Process Update Register, offset: 0x144 */ 89 __I uint32_t PRTN0_CORE0_STAT; /**< Partition 0 Core 0 Status Register, offset: 0x148 */ 90 __IO uint32_t PRTN0_CORE0_ADDR; /**< Partition 0 Core 0 Address Register, offset: 0x14C */ 91 uint8_t RESERVED_4[56]; 92 __I uint32_t PRTN0_CORE2_STAT; /**< Partition 0 Core 2 Status Register, offset: 0x188 */ 93 __I uint32_t PRTN0_CORE2_ADDR; /**< Partition 0 Core 2 Address Register, offset: 0x18C */ 94 uint8_t RESERVED_5[368]; 95 __IO uint32_t PRTN1_PCONF; /**< Partition 1 Process Configuration Register, offset: 0x300 */ 96 __IO uint32_t PRTN1_PUPD; /**< Partition 1 Process Update Register, offset: 0x304 */ 97 __I uint32_t PRTN1_STAT; /**< Partition 1 Status Register, offset: 0x308 */ 98 uint8_t RESERVED_6[4]; 99 __I uint32_t PRTN1_COFB0_STAT; /**< Partition 1 COFB Set 0 Clock Status Register, offset: 0x310 */ 100 __I uint32_t PRTN1_COFB1_STAT; /**< Partition 1 COFB Set 1 Clock Status Register, offset: 0x314 */ 101 __I uint32_t PRTN1_COFB2_STAT; /**< Partition 1 COFB Set 2 Clock Status Register, offset: 0x318 */ 102 __I uint32_t PRTN1_COFB3_STAT; /**< Partition 1 COFB Set 3 Clock Status Register, offset: 0x31C */ 103 uint8_t RESERVED_7[16]; 104 __IO uint32_t PRTN1_COFB0_CLKEN; /**< Partition 1 COFB Set 0 Clock Enable Register, offset: 0x330 */ 105 __IO uint32_t PRTN1_COFB1_CLKEN; /**< Partition 1 COFB Set 1 Clock Enable Register, offset: 0x334 */ 106 __IO uint32_t PRTN1_COFB2_CLKEN; /**< Partition 1 COFB Set 2 Clock Enable Register, offset: 0x338 */ 107 __IO uint32_t PRTN1_COFB3_CLKEN; /**< Partition 1 COFB Set 3 Clock Enable Register, offset: 0x33C */ 108 uint8_t RESERVED_8[448]; 109 __IO uint32_t PRTN2_PCONF; /**< Partition 2 Process Configuration Register, offset: 0x500 */ 110 __IO uint32_t PRTN2_PUPD; /**< Partition 2 Process Update Register, offset: 0x504 */ 111 __I uint32_t PRTN2_STAT; /**< Partition 2 Status Register, offset: 0x508 */ 112 uint8_t RESERVED_9[4]; 113 __I uint32_t PRTN2_COFB0_STAT; /**< Partition 2 COFB Set 0 Clock Status Register, offset: 0x510 */ 114 __I uint32_t PRTN2_COFB1_STAT; /**< Partition 2 COFB Set 1 Clock Status Register, offset: 0x514 */ 115 uint8_t RESERVED_10[24]; 116 __IO uint32_t PRTN2_COFB0_CLKEN; /**< Partition 2 COFB Set 0 Clock Enable Register, offset: 0x530 */ 117 __IO uint32_t PRTN2_COFB1_CLKEN; /**< Partition 2 COFB Set 1 Clock Enable Register, offset: 0x534 */ 118 } MC_ME_Type, *MC_ME_MemMapPtr; 119 120 /** Number of instances of the MC_ME module. */ 121 #define MC_ME_INSTANCE_COUNT (1u) 122 123 /* MC_ME - Peripheral instance base addresses */ 124 /** Peripheral MC_ME base address */ 125 #define IP_MC_ME_BASE (0x402DC000u) 126 /** Peripheral MC_ME base pointer */ 127 #define IP_MC_ME ((MC_ME_Type *)IP_MC_ME_BASE) 128 /** Array initializer of MC_ME peripheral base addresses */ 129 #define IP_MC_ME_BASE_ADDRS { IP_MC_ME_BASE } 130 /** Array initializer of MC_ME peripheral base pointers */ 131 #define IP_MC_ME_BASE_PTRS { IP_MC_ME } 132 133 /* ---------------------------------------------------------------------------- 134 -- MC_ME Register Masks 135 ---------------------------------------------------------------------------- */ 136 137 /*! 138 * @addtogroup MC_ME_Register_Masks MC_ME Register Masks 139 * @{ 140 */ 141 142 /*! @name CTL_KEY - Control Key Register */ 143 /*! @{ */ 144 145 #define MC_ME_CTL_KEY_KEY_MASK (0xFFFFU) 146 #define MC_ME_CTL_KEY_KEY_SHIFT (0U) 147 #define MC_ME_CTL_KEY_KEY_WIDTH (16U) 148 #define MC_ME_CTL_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_CTL_KEY_KEY_SHIFT)) & MC_ME_CTL_KEY_KEY_MASK) 149 /*! @} */ 150 151 /*! @name MODE_CONF - Mode Configuration Register */ 152 /*! @{ */ 153 154 #define MC_ME_MODE_CONF_DEST_RST_MASK (0x1U) 155 #define MC_ME_MODE_CONF_DEST_RST_SHIFT (0U) 156 #define MC_ME_MODE_CONF_DEST_RST_WIDTH (1U) 157 #define MC_ME_MODE_CONF_DEST_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_CONF_DEST_RST_SHIFT)) & MC_ME_MODE_CONF_DEST_RST_MASK) 158 159 #define MC_ME_MODE_CONF_FUNC_RST_MASK (0x2U) 160 #define MC_ME_MODE_CONF_FUNC_RST_SHIFT (1U) 161 #define MC_ME_MODE_CONF_FUNC_RST_WIDTH (1U) 162 #define MC_ME_MODE_CONF_FUNC_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_CONF_FUNC_RST_SHIFT)) & MC_ME_MODE_CONF_FUNC_RST_MASK) 163 164 #define MC_ME_MODE_CONF_STANDBY_MASK (0x8000U) 165 #define MC_ME_MODE_CONF_STANDBY_SHIFT (15U) 166 #define MC_ME_MODE_CONF_STANDBY_WIDTH (1U) 167 #define MC_ME_MODE_CONF_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_CONF_STANDBY_SHIFT)) & MC_ME_MODE_CONF_STANDBY_MASK) 168 /*! @} */ 169 170 /*! @name MODE_UPD - Mode Update Register */ 171 /*! @{ */ 172 173 #define MC_ME_MODE_UPD_MODE_UPD_MASK (0x1U) 174 #define MC_ME_MODE_UPD_MODE_UPD_SHIFT (0U) 175 #define MC_ME_MODE_UPD_MODE_UPD_WIDTH (1U) 176 #define MC_ME_MODE_UPD_MODE_UPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_UPD_MODE_UPD_SHIFT)) & MC_ME_MODE_UPD_MODE_UPD_MASK) 177 /*! @} */ 178 179 /*! @name MODE_STAT - Mode Status Register */ 180 /*! @{ */ 181 182 #define MC_ME_MODE_STAT_PREV_MODE_MASK (0x1U) 183 #define MC_ME_MODE_STAT_PREV_MODE_SHIFT (0U) 184 #define MC_ME_MODE_STAT_PREV_MODE_WIDTH (1U) 185 #define MC_ME_MODE_STAT_PREV_MODE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MODE_STAT_PREV_MODE_SHIFT)) & MC_ME_MODE_STAT_PREV_MODE_MASK) 186 /*! @} */ 187 188 /*! @name MAIN_COREID - Main Core ID Register */ 189 /*! @{ */ 190 191 #define MC_ME_MAIN_COREID_CIDX_MASK (0x7U) 192 #define MC_ME_MAIN_COREID_CIDX_SHIFT (0U) 193 #define MC_ME_MAIN_COREID_CIDX_WIDTH (3U) 194 #define MC_ME_MAIN_COREID_CIDX(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MAIN_COREID_CIDX_SHIFT)) & MC_ME_MAIN_COREID_CIDX_MASK) 195 196 #define MC_ME_MAIN_COREID_PIDX_MASK (0x1F00U) 197 #define MC_ME_MAIN_COREID_PIDX_SHIFT (8U) 198 #define MC_ME_MAIN_COREID_PIDX_WIDTH (5U) 199 #define MC_ME_MAIN_COREID_PIDX(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_MAIN_COREID_PIDX_SHIFT)) & MC_ME_MAIN_COREID_PIDX_MASK) 200 /*! @} */ 201 202 /*! @name PRTN0_PCONF - Partition 0 Process Configuration Register */ 203 /*! @{ */ 204 205 #define MC_ME_PRTN0_PCONF_PCE_MASK (0x1U) 206 #define MC_ME_PRTN0_PCONF_PCE_SHIFT (0U) 207 #define MC_ME_PRTN0_PCONF_PCE_WIDTH (1U) 208 #define MC_ME_PRTN0_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_PCONF_PCE_SHIFT)) & MC_ME_PRTN0_PCONF_PCE_MASK) 209 /*! @} */ 210 211 /*! @name PRTN0_PUPD - Partition 0 Process Update Register */ 212 /*! @{ */ 213 214 #define MC_ME_PRTN0_PUPD_PCUD_MASK (0x1U) 215 #define MC_ME_PRTN0_PUPD_PCUD_SHIFT (0U) 216 #define MC_ME_PRTN0_PUPD_PCUD_WIDTH (1U) 217 #define MC_ME_PRTN0_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_PUPD_PCUD_SHIFT)) & MC_ME_PRTN0_PUPD_PCUD_MASK) 218 /*! @} */ 219 220 /*! @name PRTN0_STAT - Partition 0 Status Register */ 221 /*! @{ */ 222 223 #define MC_ME_PRTN0_STAT_PCS_MASK (0x1U) 224 #define MC_ME_PRTN0_STAT_PCS_SHIFT (0U) 225 #define MC_ME_PRTN0_STAT_PCS_WIDTH (1U) 226 #define MC_ME_PRTN0_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_STAT_PCS_SHIFT)) & MC_ME_PRTN0_STAT_PCS_MASK) 227 /*! @} */ 228 229 /*! @name PRTN0_COFB1_STAT - Partition 0 COFB Set 1 Clock Status Register */ 230 /*! @{ */ 231 232 #define MC_ME_PRTN0_COFB1_STAT_BLOCK32_MASK (0x1U) 233 #define MC_ME_PRTN0_COFB1_STAT_BLOCK32_SHIFT (0U) 234 #define MC_ME_PRTN0_COFB1_STAT_BLOCK32_WIDTH (1U) 235 #define MC_ME_PRTN0_COFB1_STAT_BLOCK32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK32_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK32_MASK) 236 237 #define MC_ME_PRTN0_COFB1_STAT_BLOCK33_MASK (0x2U) 238 #define MC_ME_PRTN0_COFB1_STAT_BLOCK33_SHIFT (1U) 239 #define MC_ME_PRTN0_COFB1_STAT_BLOCK33_WIDTH (1U) 240 #define MC_ME_PRTN0_COFB1_STAT_BLOCK33(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK33_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK33_MASK) 241 242 #define MC_ME_PRTN0_COFB1_STAT_BLOCK34_MASK (0x4U) 243 #define MC_ME_PRTN0_COFB1_STAT_BLOCK34_SHIFT (2U) 244 #define MC_ME_PRTN0_COFB1_STAT_BLOCK34_WIDTH (1U) 245 #define MC_ME_PRTN0_COFB1_STAT_BLOCK34(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK34_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK34_MASK) 246 247 #define MC_ME_PRTN0_COFB1_STAT_BLOCK35_MASK (0x8U) 248 #define MC_ME_PRTN0_COFB1_STAT_BLOCK35_SHIFT (3U) 249 #define MC_ME_PRTN0_COFB1_STAT_BLOCK35_WIDTH (1U) 250 #define MC_ME_PRTN0_COFB1_STAT_BLOCK35(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK35_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK35_MASK) 251 252 #define MC_ME_PRTN0_COFB1_STAT_BLOCK36_MASK (0x10U) 253 #define MC_ME_PRTN0_COFB1_STAT_BLOCK36_SHIFT (4U) 254 #define MC_ME_PRTN0_COFB1_STAT_BLOCK36_WIDTH (1U) 255 #define MC_ME_PRTN0_COFB1_STAT_BLOCK36(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK36_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK36_MASK) 256 257 #define MC_ME_PRTN0_COFB1_STAT_BLOCK38_MASK (0x40U) 258 #define MC_ME_PRTN0_COFB1_STAT_BLOCK38_SHIFT (6U) 259 #define MC_ME_PRTN0_COFB1_STAT_BLOCK38_WIDTH (1U) 260 #define MC_ME_PRTN0_COFB1_STAT_BLOCK38(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK38_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK38_MASK) 261 262 #define MC_ME_PRTN0_COFB1_STAT_BLOCK39_MASK (0x80U) 263 #define MC_ME_PRTN0_COFB1_STAT_BLOCK39_SHIFT (7U) 264 #define MC_ME_PRTN0_COFB1_STAT_BLOCK39_WIDTH (1U) 265 #define MC_ME_PRTN0_COFB1_STAT_BLOCK39(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK39_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK39_MASK) 266 267 #define MC_ME_PRTN0_COFB1_STAT_BLOCK40_MASK (0x100U) 268 #define MC_ME_PRTN0_COFB1_STAT_BLOCK40_SHIFT (8U) 269 #define MC_ME_PRTN0_COFB1_STAT_BLOCK40_WIDTH (1U) 270 #define MC_ME_PRTN0_COFB1_STAT_BLOCK40(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK40_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK40_MASK) 271 272 #define MC_ME_PRTN0_COFB1_STAT_BLOCK41_MASK (0x200U) 273 #define MC_ME_PRTN0_COFB1_STAT_BLOCK41_SHIFT (9U) 274 #define MC_ME_PRTN0_COFB1_STAT_BLOCK41_WIDTH (1U) 275 #define MC_ME_PRTN0_COFB1_STAT_BLOCK41(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK41_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK41_MASK) 276 277 #define MC_ME_PRTN0_COFB1_STAT_BLOCK42_MASK (0x400U) 278 #define MC_ME_PRTN0_COFB1_STAT_BLOCK42_SHIFT (10U) 279 #define MC_ME_PRTN0_COFB1_STAT_BLOCK42_WIDTH (1U) 280 #define MC_ME_PRTN0_COFB1_STAT_BLOCK42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK42_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK42_MASK) 281 282 #define MC_ME_PRTN0_COFB1_STAT_BLOCK44_MASK (0x1000U) 283 #define MC_ME_PRTN0_COFB1_STAT_BLOCK44_SHIFT (12U) 284 #define MC_ME_PRTN0_COFB1_STAT_BLOCK44_WIDTH (1U) 285 #define MC_ME_PRTN0_COFB1_STAT_BLOCK44(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK44_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK44_MASK) 286 287 #define MC_ME_PRTN0_COFB1_STAT_BLOCK45_MASK (0x2000U) 288 #define MC_ME_PRTN0_COFB1_STAT_BLOCK45_SHIFT (13U) 289 #define MC_ME_PRTN0_COFB1_STAT_BLOCK45_WIDTH (1U) 290 #define MC_ME_PRTN0_COFB1_STAT_BLOCK45(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK45_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK45_MASK) 291 292 #define MC_ME_PRTN0_COFB1_STAT_BLOCK46_MASK (0x4000U) 293 #define MC_ME_PRTN0_COFB1_STAT_BLOCK46_SHIFT (14U) 294 #define MC_ME_PRTN0_COFB1_STAT_BLOCK46_WIDTH (1U) 295 #define MC_ME_PRTN0_COFB1_STAT_BLOCK46(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK46_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK46_MASK) 296 297 #define MC_ME_PRTN0_COFB1_STAT_BLOCK47_MASK (0x8000U) 298 #define MC_ME_PRTN0_COFB1_STAT_BLOCK47_SHIFT (15U) 299 #define MC_ME_PRTN0_COFB1_STAT_BLOCK47_WIDTH (1U) 300 #define MC_ME_PRTN0_COFB1_STAT_BLOCK47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_STAT_BLOCK47_SHIFT)) & MC_ME_PRTN0_COFB1_STAT_BLOCK47_MASK) 301 /*! @} */ 302 303 /*! @name PRTN0_COFB1_CLKEN - Partition 0 COFB Set 1 Clock Enable Register */ 304 /*! @{ */ 305 306 #define MC_ME_PRTN0_COFB1_CLKEN_REQ32_MASK (0x1U) 307 #define MC_ME_PRTN0_COFB1_CLKEN_REQ32_SHIFT (0U) 308 #define MC_ME_PRTN0_COFB1_CLKEN_REQ32_WIDTH (1U) 309 #define MC_ME_PRTN0_COFB1_CLKEN_REQ32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ32_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ32_MASK) 310 311 #define MC_ME_PRTN0_COFB1_CLKEN_REQ33_MASK (0x2U) 312 #define MC_ME_PRTN0_COFB1_CLKEN_REQ33_SHIFT (1U) 313 #define MC_ME_PRTN0_COFB1_CLKEN_REQ33_WIDTH (1U) 314 #define MC_ME_PRTN0_COFB1_CLKEN_REQ33(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ33_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ33_MASK) 315 316 #define MC_ME_PRTN0_COFB1_CLKEN_REQ34_MASK (0x4U) 317 #define MC_ME_PRTN0_COFB1_CLKEN_REQ34_SHIFT (2U) 318 #define MC_ME_PRTN0_COFB1_CLKEN_REQ34_WIDTH (1U) 319 #define MC_ME_PRTN0_COFB1_CLKEN_REQ34(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ34_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ34_MASK) 320 321 #define MC_ME_PRTN0_COFB1_CLKEN_REQ35_MASK (0x8U) 322 #define MC_ME_PRTN0_COFB1_CLKEN_REQ35_SHIFT (3U) 323 #define MC_ME_PRTN0_COFB1_CLKEN_REQ35_WIDTH (1U) 324 #define MC_ME_PRTN0_COFB1_CLKEN_REQ35(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ35_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ35_MASK) 325 326 #define MC_ME_PRTN0_COFB1_CLKEN_REQ36_MASK (0x10U) 327 #define MC_ME_PRTN0_COFB1_CLKEN_REQ36_SHIFT (4U) 328 #define MC_ME_PRTN0_COFB1_CLKEN_REQ36_WIDTH (1U) 329 #define MC_ME_PRTN0_COFB1_CLKEN_REQ36(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ36_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ36_MASK) 330 331 #define MC_ME_PRTN0_COFB1_CLKEN_REQ38_MASK (0x40U) 332 #define MC_ME_PRTN0_COFB1_CLKEN_REQ38_SHIFT (6U) 333 #define MC_ME_PRTN0_COFB1_CLKEN_REQ38_WIDTH (1U) 334 #define MC_ME_PRTN0_COFB1_CLKEN_REQ38(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ38_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ38_MASK) 335 336 #define MC_ME_PRTN0_COFB1_CLKEN_REQ39_MASK (0x80U) 337 #define MC_ME_PRTN0_COFB1_CLKEN_REQ39_SHIFT (7U) 338 #define MC_ME_PRTN0_COFB1_CLKEN_REQ39_WIDTH (1U) 339 #define MC_ME_PRTN0_COFB1_CLKEN_REQ39(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ39_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ39_MASK) 340 341 #define MC_ME_PRTN0_COFB1_CLKEN_REQ40_MASK (0x100U) 342 #define MC_ME_PRTN0_COFB1_CLKEN_REQ40_SHIFT (8U) 343 #define MC_ME_PRTN0_COFB1_CLKEN_REQ40_WIDTH (1U) 344 #define MC_ME_PRTN0_COFB1_CLKEN_REQ40(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ40_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ40_MASK) 345 346 #define MC_ME_PRTN0_COFB1_CLKEN_REQ41_MASK (0x200U) 347 #define MC_ME_PRTN0_COFB1_CLKEN_REQ41_SHIFT (9U) 348 #define MC_ME_PRTN0_COFB1_CLKEN_REQ41_WIDTH (1U) 349 #define MC_ME_PRTN0_COFB1_CLKEN_REQ41(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ41_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ41_MASK) 350 351 #define MC_ME_PRTN0_COFB1_CLKEN_REQ42_MASK (0x400U) 352 #define MC_ME_PRTN0_COFB1_CLKEN_REQ42_SHIFT (10U) 353 #define MC_ME_PRTN0_COFB1_CLKEN_REQ42_WIDTH (1U) 354 #define MC_ME_PRTN0_COFB1_CLKEN_REQ42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ42_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ42_MASK) 355 356 #define MC_ME_PRTN0_COFB1_CLKEN_REQ44_MASK (0x1000U) 357 #define MC_ME_PRTN0_COFB1_CLKEN_REQ44_SHIFT (12U) 358 #define MC_ME_PRTN0_COFB1_CLKEN_REQ44_WIDTH (1U) 359 #define MC_ME_PRTN0_COFB1_CLKEN_REQ44(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ44_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ44_MASK) 360 361 #define MC_ME_PRTN0_COFB1_CLKEN_REQ45_MASK (0x2000U) 362 #define MC_ME_PRTN0_COFB1_CLKEN_REQ45_SHIFT (13U) 363 #define MC_ME_PRTN0_COFB1_CLKEN_REQ45_WIDTH (1U) 364 #define MC_ME_PRTN0_COFB1_CLKEN_REQ45(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ45_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ45_MASK) 365 366 #define MC_ME_PRTN0_COFB1_CLKEN_REQ46_MASK (0x4000U) 367 #define MC_ME_PRTN0_COFB1_CLKEN_REQ46_SHIFT (14U) 368 #define MC_ME_PRTN0_COFB1_CLKEN_REQ46_WIDTH (1U) 369 #define MC_ME_PRTN0_COFB1_CLKEN_REQ46(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ46_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ46_MASK) 370 371 #define MC_ME_PRTN0_COFB1_CLKEN_REQ47_MASK (0x8000U) 372 #define MC_ME_PRTN0_COFB1_CLKEN_REQ47_SHIFT (15U) 373 #define MC_ME_PRTN0_COFB1_CLKEN_REQ47_WIDTH (1U) 374 #define MC_ME_PRTN0_COFB1_CLKEN_REQ47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_COFB1_CLKEN_REQ47_SHIFT)) & MC_ME_PRTN0_COFB1_CLKEN_REQ47_MASK) 375 /*! @} */ 376 377 /*! @name PRTN0_CORE0_PCONF - Partition 0 Core 0 Process Configuration Register */ 378 /*! @{ */ 379 380 #define MC_ME_PRTN0_CORE0_PCONF_CCE_MASK (0x1U) 381 #define MC_ME_PRTN0_CORE0_PCONF_CCE_SHIFT (0U) 382 #define MC_ME_PRTN0_CORE0_PCONF_CCE_WIDTH (1U) 383 #define MC_ME_PRTN0_CORE0_PCONF_CCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_PCONF_CCE_SHIFT)) & MC_ME_PRTN0_CORE0_PCONF_CCE_MASK) 384 /*! @} */ 385 386 /*! @name PRTN0_CORE0_PUPD - Partition 0 Core 0 Process Update Register */ 387 /*! @{ */ 388 389 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_MASK (0x1U) 390 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_SHIFT (0U) 391 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD_WIDTH (1U) 392 #define MC_ME_PRTN0_CORE0_PUPD_CCUPD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_PUPD_CCUPD_SHIFT)) & MC_ME_PRTN0_CORE0_PUPD_CCUPD_MASK) 393 /*! @} */ 394 395 /*! @name PRTN0_CORE0_STAT - Partition 0 Core 0 Status Register */ 396 /*! @{ */ 397 398 #define MC_ME_PRTN0_CORE0_STAT_CCS_MASK (0x1U) 399 #define MC_ME_PRTN0_CORE0_STAT_CCS_SHIFT (0U) 400 #define MC_ME_PRTN0_CORE0_STAT_CCS_WIDTH (1U) 401 #define MC_ME_PRTN0_CORE0_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE0_STAT_CCS_MASK) 402 403 #define MC_ME_PRTN0_CORE0_STAT_WFI_MASK (0x80000000U) 404 #define MC_ME_PRTN0_CORE0_STAT_WFI_SHIFT (31U) 405 #define MC_ME_PRTN0_CORE0_STAT_WFI_WIDTH (1U) 406 #define MC_ME_PRTN0_CORE0_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE0_STAT_WFI_MASK) 407 /*! @} */ 408 409 /*! @name PRTN0_CORE0_ADDR - Partition 0 Core 0 Address Register */ 410 /*! @{ */ 411 412 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_MASK (0xFFFFFFFCU) 413 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_SHIFT (2U) 414 #define MC_ME_PRTN0_CORE0_ADDR_ADDR_WIDTH (30U) 415 #define MC_ME_PRTN0_CORE0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE0_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE0_ADDR_ADDR_MASK) 416 /*! @} */ 417 418 /*! @name PRTN0_CORE2_STAT - Partition 0 Core 2 Status Register */ 419 /*! @{ */ 420 421 #define MC_ME_PRTN0_CORE2_STAT_CCS_MASK (0x1U) 422 #define MC_ME_PRTN0_CORE2_STAT_CCS_SHIFT (0U) 423 #define MC_ME_PRTN0_CORE2_STAT_CCS_WIDTH (1U) 424 #define MC_ME_PRTN0_CORE2_STAT_CCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_STAT_CCS_SHIFT)) & MC_ME_PRTN0_CORE2_STAT_CCS_MASK) 425 426 #define MC_ME_PRTN0_CORE2_STAT_WFI_MASK (0x80000000U) 427 #define MC_ME_PRTN0_CORE2_STAT_WFI_SHIFT (31U) 428 #define MC_ME_PRTN0_CORE2_STAT_WFI_WIDTH (1U) 429 #define MC_ME_PRTN0_CORE2_STAT_WFI(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_STAT_WFI_SHIFT)) & MC_ME_PRTN0_CORE2_STAT_WFI_MASK) 430 /*! @} */ 431 432 /*! @name PRTN0_CORE2_ADDR - Partition 0 Core 2 Address Register */ 433 /*! @{ */ 434 435 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_MASK (0xFFFFFFFCU) 436 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_SHIFT (2U) 437 #define MC_ME_PRTN0_CORE2_ADDR_ADDR_WIDTH (30U) 438 #define MC_ME_PRTN0_CORE2_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN0_CORE2_ADDR_ADDR_SHIFT)) & MC_ME_PRTN0_CORE2_ADDR_ADDR_MASK) 439 /*! @} */ 440 441 /*! @name PRTN1_PCONF - Partition 1 Process Configuration Register */ 442 /*! @{ */ 443 444 #define MC_ME_PRTN1_PCONF_PCE_MASK (0x1U) 445 #define MC_ME_PRTN1_PCONF_PCE_SHIFT (0U) 446 #define MC_ME_PRTN1_PCONF_PCE_WIDTH (1U) 447 #define MC_ME_PRTN1_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PCONF_PCE_SHIFT)) & MC_ME_PRTN1_PCONF_PCE_MASK) 448 /*! @} */ 449 450 /*! @name PRTN1_PUPD - Partition 1 Process Update Register */ 451 /*! @{ */ 452 453 #define MC_ME_PRTN1_PUPD_PCUD_MASK (0x1U) 454 #define MC_ME_PRTN1_PUPD_PCUD_SHIFT (0U) 455 #define MC_ME_PRTN1_PUPD_PCUD_WIDTH (1U) 456 #define MC_ME_PRTN1_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_PUPD_PCUD_SHIFT)) & MC_ME_PRTN1_PUPD_PCUD_MASK) 457 /*! @} */ 458 459 /*! @name PRTN1_STAT - Partition 1 Status Register */ 460 /*! @{ */ 461 462 #define MC_ME_PRTN1_STAT_PCS_MASK (0x1U) 463 #define MC_ME_PRTN1_STAT_PCS_SHIFT (0U) 464 #define MC_ME_PRTN1_STAT_PCS_WIDTH (1U) 465 #define MC_ME_PRTN1_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_STAT_PCS_SHIFT)) & MC_ME_PRTN1_STAT_PCS_MASK) 466 /*! @} */ 467 468 /*! @name PRTN1_COFB0_STAT - Partition 1 COFB Set 0 Clock Status Register */ 469 /*! @{ */ 470 471 #define MC_ME_PRTN1_COFB0_STAT_BLOCK0_MASK (0x1U) 472 #define MC_ME_PRTN1_COFB0_STAT_BLOCK0_SHIFT (0U) 473 #define MC_ME_PRTN1_COFB0_STAT_BLOCK0_WIDTH (1U) 474 #define MC_ME_PRTN1_COFB0_STAT_BLOCK0(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK0_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK0_MASK) 475 476 #define MC_ME_PRTN1_COFB0_STAT_BLOCK1_MASK (0x2U) 477 #define MC_ME_PRTN1_COFB0_STAT_BLOCK1_SHIFT (1U) 478 #define MC_ME_PRTN1_COFB0_STAT_BLOCK1_WIDTH (1U) 479 #define MC_ME_PRTN1_COFB0_STAT_BLOCK1(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK1_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK1_MASK) 480 481 #define MC_ME_PRTN1_COFB0_STAT_BLOCK2_MASK (0x4U) 482 #define MC_ME_PRTN1_COFB0_STAT_BLOCK2_SHIFT (2U) 483 #define MC_ME_PRTN1_COFB0_STAT_BLOCK2_WIDTH (1U) 484 #define MC_ME_PRTN1_COFB0_STAT_BLOCK2(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK2_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK2_MASK) 485 486 #define MC_ME_PRTN1_COFB0_STAT_BLOCK3_MASK (0x8U) 487 #define MC_ME_PRTN1_COFB0_STAT_BLOCK3_SHIFT (3U) 488 #define MC_ME_PRTN1_COFB0_STAT_BLOCK3_WIDTH (1U) 489 #define MC_ME_PRTN1_COFB0_STAT_BLOCK3(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK3_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK3_MASK) 490 491 #define MC_ME_PRTN1_COFB0_STAT_BLOCK4_MASK (0x10U) 492 #define MC_ME_PRTN1_COFB0_STAT_BLOCK4_SHIFT (4U) 493 #define MC_ME_PRTN1_COFB0_STAT_BLOCK4_WIDTH (1U) 494 #define MC_ME_PRTN1_COFB0_STAT_BLOCK4(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK4_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK4_MASK) 495 496 #define MC_ME_PRTN1_COFB0_STAT_BLOCK5_MASK (0x20U) 497 #define MC_ME_PRTN1_COFB0_STAT_BLOCK5_SHIFT (5U) 498 #define MC_ME_PRTN1_COFB0_STAT_BLOCK5_WIDTH (1U) 499 #define MC_ME_PRTN1_COFB0_STAT_BLOCK5(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK5_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK5_MASK) 500 501 #define MC_ME_PRTN1_COFB0_STAT_BLOCK6_MASK (0x40U) 502 #define MC_ME_PRTN1_COFB0_STAT_BLOCK6_SHIFT (6U) 503 #define MC_ME_PRTN1_COFB0_STAT_BLOCK6_WIDTH (1U) 504 #define MC_ME_PRTN1_COFB0_STAT_BLOCK6(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK6_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK6_MASK) 505 506 #define MC_ME_PRTN1_COFB0_STAT_BLOCK7_MASK (0x80U) 507 #define MC_ME_PRTN1_COFB0_STAT_BLOCK7_SHIFT (7U) 508 #define MC_ME_PRTN1_COFB0_STAT_BLOCK7_WIDTH (1U) 509 #define MC_ME_PRTN1_COFB0_STAT_BLOCK7(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK7_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK7_MASK) 510 511 #define MC_ME_PRTN1_COFB0_STAT_BLOCK8_MASK (0x100U) 512 #define MC_ME_PRTN1_COFB0_STAT_BLOCK8_SHIFT (8U) 513 #define MC_ME_PRTN1_COFB0_STAT_BLOCK8_WIDTH (1U) 514 #define MC_ME_PRTN1_COFB0_STAT_BLOCK8(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK8_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK8_MASK) 515 516 #define MC_ME_PRTN1_COFB0_STAT_BLOCK9_MASK (0x200U) 517 #define MC_ME_PRTN1_COFB0_STAT_BLOCK9_SHIFT (9U) 518 #define MC_ME_PRTN1_COFB0_STAT_BLOCK9_WIDTH (1U) 519 #define MC_ME_PRTN1_COFB0_STAT_BLOCK9(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK9_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK9_MASK) 520 521 #define MC_ME_PRTN1_COFB0_STAT_BLOCK10_MASK (0x400U) 522 #define MC_ME_PRTN1_COFB0_STAT_BLOCK10_SHIFT (10U) 523 #define MC_ME_PRTN1_COFB0_STAT_BLOCK10_WIDTH (1U) 524 #define MC_ME_PRTN1_COFB0_STAT_BLOCK10(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK10_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK10_MASK) 525 526 #define MC_ME_PRTN1_COFB0_STAT_BLOCK11_MASK (0x800U) 527 #define MC_ME_PRTN1_COFB0_STAT_BLOCK11_SHIFT (11U) 528 #define MC_ME_PRTN1_COFB0_STAT_BLOCK11_WIDTH (1U) 529 #define MC_ME_PRTN1_COFB0_STAT_BLOCK11(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK11_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK11_MASK) 530 531 #define MC_ME_PRTN1_COFB0_STAT_BLOCK12_MASK (0x1000U) 532 #define MC_ME_PRTN1_COFB0_STAT_BLOCK12_SHIFT (12U) 533 #define MC_ME_PRTN1_COFB0_STAT_BLOCK12_WIDTH (1U) 534 #define MC_ME_PRTN1_COFB0_STAT_BLOCK12(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK12_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK12_MASK) 535 536 #define MC_ME_PRTN1_COFB0_STAT_BLOCK13_MASK (0x2000U) 537 #define MC_ME_PRTN1_COFB0_STAT_BLOCK13_SHIFT (13U) 538 #define MC_ME_PRTN1_COFB0_STAT_BLOCK13_WIDTH (1U) 539 #define MC_ME_PRTN1_COFB0_STAT_BLOCK13(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK13_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK13_MASK) 540 541 #define MC_ME_PRTN1_COFB0_STAT_BLOCK14_MASK (0x4000U) 542 #define MC_ME_PRTN1_COFB0_STAT_BLOCK14_SHIFT (14U) 543 #define MC_ME_PRTN1_COFB0_STAT_BLOCK14_WIDTH (1U) 544 #define MC_ME_PRTN1_COFB0_STAT_BLOCK14(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK14_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK14_MASK) 545 546 #define MC_ME_PRTN1_COFB0_STAT_BLOCK15_MASK (0x8000U) 547 #define MC_ME_PRTN1_COFB0_STAT_BLOCK15_SHIFT (15U) 548 #define MC_ME_PRTN1_COFB0_STAT_BLOCK15_WIDTH (1U) 549 #define MC_ME_PRTN1_COFB0_STAT_BLOCK15(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK15_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK15_MASK) 550 551 #define MC_ME_PRTN1_COFB0_STAT_BLOCK16_MASK (0x10000U) 552 #define MC_ME_PRTN1_COFB0_STAT_BLOCK16_SHIFT (16U) 553 #define MC_ME_PRTN1_COFB0_STAT_BLOCK16_WIDTH (1U) 554 #define MC_ME_PRTN1_COFB0_STAT_BLOCK16(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK16_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK16_MASK) 555 556 #define MC_ME_PRTN1_COFB0_STAT_BLOCK17_MASK (0x20000U) 557 #define MC_ME_PRTN1_COFB0_STAT_BLOCK17_SHIFT (17U) 558 #define MC_ME_PRTN1_COFB0_STAT_BLOCK17_WIDTH (1U) 559 #define MC_ME_PRTN1_COFB0_STAT_BLOCK17(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK17_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK17_MASK) 560 561 #define MC_ME_PRTN1_COFB0_STAT_BLOCK18_MASK (0x40000U) 562 #define MC_ME_PRTN1_COFB0_STAT_BLOCK18_SHIFT (18U) 563 #define MC_ME_PRTN1_COFB0_STAT_BLOCK18_WIDTH (1U) 564 #define MC_ME_PRTN1_COFB0_STAT_BLOCK18(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK18_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK18_MASK) 565 566 #define MC_ME_PRTN1_COFB0_STAT_BLOCK19_MASK (0x80000U) 567 #define MC_ME_PRTN1_COFB0_STAT_BLOCK19_SHIFT (19U) 568 #define MC_ME_PRTN1_COFB0_STAT_BLOCK19_WIDTH (1U) 569 #define MC_ME_PRTN1_COFB0_STAT_BLOCK19(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK19_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK19_MASK) 570 571 #define MC_ME_PRTN1_COFB0_STAT_BLOCK20_MASK (0x100000U) 572 #define MC_ME_PRTN1_COFB0_STAT_BLOCK20_SHIFT (20U) 573 #define MC_ME_PRTN1_COFB0_STAT_BLOCK20_WIDTH (1U) 574 #define MC_ME_PRTN1_COFB0_STAT_BLOCK20(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK20_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK20_MASK) 575 576 #define MC_ME_PRTN1_COFB0_STAT_BLOCK21_MASK (0x200000U) 577 #define MC_ME_PRTN1_COFB0_STAT_BLOCK21_SHIFT (21U) 578 #define MC_ME_PRTN1_COFB0_STAT_BLOCK21_WIDTH (1U) 579 #define MC_ME_PRTN1_COFB0_STAT_BLOCK21(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK21_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK21_MASK) 580 581 #define MC_ME_PRTN1_COFB0_STAT_BLOCK22_MASK (0x400000U) 582 #define MC_ME_PRTN1_COFB0_STAT_BLOCK22_SHIFT (22U) 583 #define MC_ME_PRTN1_COFB0_STAT_BLOCK22_WIDTH (1U) 584 #define MC_ME_PRTN1_COFB0_STAT_BLOCK22(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK22_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK22_MASK) 585 586 #define MC_ME_PRTN1_COFB0_STAT_BLOCK23_MASK (0x800000U) 587 #define MC_ME_PRTN1_COFB0_STAT_BLOCK23_SHIFT (23U) 588 #define MC_ME_PRTN1_COFB0_STAT_BLOCK23_WIDTH (1U) 589 #define MC_ME_PRTN1_COFB0_STAT_BLOCK23(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK23_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK23_MASK) 590 591 #define MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK (0x1000000U) 592 #define MC_ME_PRTN1_COFB0_STAT_BLOCK24_SHIFT (24U) 593 #define MC_ME_PRTN1_COFB0_STAT_BLOCK24_WIDTH (1U) 594 #define MC_ME_PRTN1_COFB0_STAT_BLOCK24(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK24_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK) 595 596 #define MC_ME_PRTN1_COFB0_STAT_BLOCK25_MASK (0x2000000U) 597 #define MC_ME_PRTN1_COFB0_STAT_BLOCK25_SHIFT (25U) 598 #define MC_ME_PRTN1_COFB0_STAT_BLOCK25_WIDTH (1U) 599 #define MC_ME_PRTN1_COFB0_STAT_BLOCK25(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK25_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK25_MASK) 600 601 #define MC_ME_PRTN1_COFB0_STAT_BLOCK26_MASK (0x4000000U) 602 #define MC_ME_PRTN1_COFB0_STAT_BLOCK26_SHIFT (26U) 603 #define MC_ME_PRTN1_COFB0_STAT_BLOCK26_WIDTH (1U) 604 #define MC_ME_PRTN1_COFB0_STAT_BLOCK26(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK26_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK26_MASK) 605 606 #define MC_ME_PRTN1_COFB0_STAT_BLOCK27_MASK (0x8000000U) 607 #define MC_ME_PRTN1_COFB0_STAT_BLOCK27_SHIFT (27U) 608 #define MC_ME_PRTN1_COFB0_STAT_BLOCK27_WIDTH (1U) 609 #define MC_ME_PRTN1_COFB0_STAT_BLOCK27(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK27_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK27_MASK) 610 611 #define MC_ME_PRTN1_COFB0_STAT_BLOCK28_MASK (0x10000000U) 612 #define MC_ME_PRTN1_COFB0_STAT_BLOCK28_SHIFT (28U) 613 #define MC_ME_PRTN1_COFB0_STAT_BLOCK28_WIDTH (1U) 614 #define MC_ME_PRTN1_COFB0_STAT_BLOCK28(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK28_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK28_MASK) 615 616 #define MC_ME_PRTN1_COFB0_STAT_BLOCK29_MASK (0x20000000U) 617 #define MC_ME_PRTN1_COFB0_STAT_BLOCK29_SHIFT (29U) 618 #define MC_ME_PRTN1_COFB0_STAT_BLOCK29_WIDTH (1U) 619 #define MC_ME_PRTN1_COFB0_STAT_BLOCK29(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK29_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK29_MASK) 620 621 #define MC_ME_PRTN1_COFB0_STAT_BLOCK30_MASK (0x40000000U) 622 #define MC_ME_PRTN1_COFB0_STAT_BLOCK30_SHIFT (30U) 623 #define MC_ME_PRTN1_COFB0_STAT_BLOCK30_WIDTH (1U) 624 #define MC_ME_PRTN1_COFB0_STAT_BLOCK30(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK30_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK30_MASK) 625 626 #define MC_ME_PRTN1_COFB0_STAT_BLOCK31_MASK (0x80000000U) 627 #define MC_ME_PRTN1_COFB0_STAT_BLOCK31_SHIFT (31U) 628 #define MC_ME_PRTN1_COFB0_STAT_BLOCK31_WIDTH (1U) 629 #define MC_ME_PRTN1_COFB0_STAT_BLOCK31(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_STAT_BLOCK31_SHIFT)) & MC_ME_PRTN1_COFB0_STAT_BLOCK31_MASK) 630 /*! @} */ 631 632 /*! @name PRTN1_COFB1_STAT - Partition 1 COFB Set 1 Clock Status Register */ 633 /*! @{ */ 634 635 #define MC_ME_PRTN1_COFB1_STAT_BLOCK32_MASK (0x1U) 636 #define MC_ME_PRTN1_COFB1_STAT_BLOCK32_SHIFT (0U) 637 #define MC_ME_PRTN1_COFB1_STAT_BLOCK32_WIDTH (1U) 638 #define MC_ME_PRTN1_COFB1_STAT_BLOCK32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK32_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK32_MASK) 639 640 #define MC_ME_PRTN1_COFB1_STAT_BLOCK33_MASK (0x2U) 641 #define MC_ME_PRTN1_COFB1_STAT_BLOCK33_SHIFT (1U) 642 #define MC_ME_PRTN1_COFB1_STAT_BLOCK33_WIDTH (1U) 643 #define MC_ME_PRTN1_COFB1_STAT_BLOCK33(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK33_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK33_MASK) 644 645 #define MC_ME_PRTN1_COFB1_STAT_BLOCK34_MASK (0x4U) 646 #define MC_ME_PRTN1_COFB1_STAT_BLOCK34_SHIFT (2U) 647 #define MC_ME_PRTN1_COFB1_STAT_BLOCK34_WIDTH (1U) 648 #define MC_ME_PRTN1_COFB1_STAT_BLOCK34(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK34_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK34_MASK) 649 650 #define MC_ME_PRTN1_COFB1_STAT_BLOCK35_MASK (0x8U) 651 #define MC_ME_PRTN1_COFB1_STAT_BLOCK35_SHIFT (3U) 652 #define MC_ME_PRTN1_COFB1_STAT_BLOCK35_WIDTH (1U) 653 #define MC_ME_PRTN1_COFB1_STAT_BLOCK35(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK35_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK35_MASK) 654 655 #define MC_ME_PRTN1_COFB1_STAT_BLOCK36_MASK (0x10U) 656 #define MC_ME_PRTN1_COFB1_STAT_BLOCK36_SHIFT (4U) 657 #define MC_ME_PRTN1_COFB1_STAT_BLOCK36_WIDTH (1U) 658 #define MC_ME_PRTN1_COFB1_STAT_BLOCK36(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK36_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK36_MASK) 659 660 #define MC_ME_PRTN1_COFB1_STAT_BLOCK37_MASK (0x20U) 661 #define MC_ME_PRTN1_COFB1_STAT_BLOCK37_SHIFT (5U) 662 #define MC_ME_PRTN1_COFB1_STAT_BLOCK37_WIDTH (1U) 663 #define MC_ME_PRTN1_COFB1_STAT_BLOCK37(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK37_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK37_MASK) 664 665 #define MC_ME_PRTN1_COFB1_STAT_BLOCK38_MASK (0x40U) 666 #define MC_ME_PRTN1_COFB1_STAT_BLOCK38_SHIFT (6U) 667 #define MC_ME_PRTN1_COFB1_STAT_BLOCK38_WIDTH (1U) 668 #define MC_ME_PRTN1_COFB1_STAT_BLOCK38(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK38_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK38_MASK) 669 670 #define MC_ME_PRTN1_COFB1_STAT_BLOCK39_MASK (0x80U) 671 #define MC_ME_PRTN1_COFB1_STAT_BLOCK39_SHIFT (7U) 672 #define MC_ME_PRTN1_COFB1_STAT_BLOCK39_WIDTH (1U) 673 #define MC_ME_PRTN1_COFB1_STAT_BLOCK39(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK39_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK39_MASK) 674 675 #define MC_ME_PRTN1_COFB1_STAT_BLOCK40_MASK (0x100U) 676 #define MC_ME_PRTN1_COFB1_STAT_BLOCK40_SHIFT (8U) 677 #define MC_ME_PRTN1_COFB1_STAT_BLOCK40_WIDTH (1U) 678 #define MC_ME_PRTN1_COFB1_STAT_BLOCK40(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK40_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK40_MASK) 679 680 #define MC_ME_PRTN1_COFB1_STAT_BLOCK41_MASK (0x200U) 681 #define MC_ME_PRTN1_COFB1_STAT_BLOCK41_SHIFT (9U) 682 #define MC_ME_PRTN1_COFB1_STAT_BLOCK41_WIDTH (1U) 683 #define MC_ME_PRTN1_COFB1_STAT_BLOCK41(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK41_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK41_MASK) 684 685 #define MC_ME_PRTN1_COFB1_STAT_BLOCK42_MASK (0x400U) 686 #define MC_ME_PRTN1_COFB1_STAT_BLOCK42_SHIFT (10U) 687 #define MC_ME_PRTN1_COFB1_STAT_BLOCK42_WIDTH (1U) 688 #define MC_ME_PRTN1_COFB1_STAT_BLOCK42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK42_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK42_MASK) 689 690 #define MC_ME_PRTN1_COFB1_STAT_BLOCK43_MASK (0x800U) 691 #define MC_ME_PRTN1_COFB1_STAT_BLOCK43_SHIFT (11U) 692 #define MC_ME_PRTN1_COFB1_STAT_BLOCK43_WIDTH (1U) 693 #define MC_ME_PRTN1_COFB1_STAT_BLOCK43(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK43_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK43_MASK) 694 695 #define MC_ME_PRTN1_COFB1_STAT_BLOCK45_MASK (0x2000U) 696 #define MC_ME_PRTN1_COFB1_STAT_BLOCK45_SHIFT (13U) 697 #define MC_ME_PRTN1_COFB1_STAT_BLOCK45_WIDTH (1U) 698 #define MC_ME_PRTN1_COFB1_STAT_BLOCK45(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK45_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK45_MASK) 699 700 #define MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK (0x8000U) 701 #define MC_ME_PRTN1_COFB1_STAT_BLOCK47_SHIFT (15U) 702 #define MC_ME_PRTN1_COFB1_STAT_BLOCK47_WIDTH (1U) 703 #define MC_ME_PRTN1_COFB1_STAT_BLOCK47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK47_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK) 704 705 #define MC_ME_PRTN1_COFB1_STAT_BLOCK49_MASK (0x20000U) 706 #define MC_ME_PRTN1_COFB1_STAT_BLOCK49_SHIFT (17U) 707 #define MC_ME_PRTN1_COFB1_STAT_BLOCK49_WIDTH (1U) 708 #define MC_ME_PRTN1_COFB1_STAT_BLOCK49(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK49_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK49_MASK) 709 710 #define MC_ME_PRTN1_COFB1_STAT_BLOCK50_MASK (0x40000U) 711 #define MC_ME_PRTN1_COFB1_STAT_BLOCK50_SHIFT (18U) 712 #define MC_ME_PRTN1_COFB1_STAT_BLOCK50_WIDTH (1U) 713 #define MC_ME_PRTN1_COFB1_STAT_BLOCK50(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK50_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK50_MASK) 714 715 #define MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK (0x80000U) 716 #define MC_ME_PRTN1_COFB1_STAT_BLOCK51_SHIFT (19U) 717 #define MC_ME_PRTN1_COFB1_STAT_BLOCK51_WIDTH (1U) 718 #define MC_ME_PRTN1_COFB1_STAT_BLOCK51(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK51_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK) 719 720 #define MC_ME_PRTN1_COFB1_STAT_BLOCK52_MASK (0x100000U) 721 #define MC_ME_PRTN1_COFB1_STAT_BLOCK52_SHIFT (20U) 722 #define MC_ME_PRTN1_COFB1_STAT_BLOCK52_WIDTH (1U) 723 #define MC_ME_PRTN1_COFB1_STAT_BLOCK52(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK52_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK52_MASK) 724 725 #define MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK (0x200000U) 726 #define MC_ME_PRTN1_COFB1_STAT_BLOCK53_SHIFT (21U) 727 #define MC_ME_PRTN1_COFB1_STAT_BLOCK53_WIDTH (1U) 728 #define MC_ME_PRTN1_COFB1_STAT_BLOCK53(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK53_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK) 729 730 #define MC_ME_PRTN1_COFB1_STAT_BLOCK54_MASK (0x400000U) 731 #define MC_ME_PRTN1_COFB1_STAT_BLOCK54_SHIFT (22U) 732 #define MC_ME_PRTN1_COFB1_STAT_BLOCK54_WIDTH (1U) 733 #define MC_ME_PRTN1_COFB1_STAT_BLOCK54(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK54_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK54_MASK) 734 735 #define MC_ME_PRTN1_COFB1_STAT_BLOCK55_MASK (0x800000U) 736 #define MC_ME_PRTN1_COFB1_STAT_BLOCK55_SHIFT (23U) 737 #define MC_ME_PRTN1_COFB1_STAT_BLOCK55_WIDTH (1U) 738 #define MC_ME_PRTN1_COFB1_STAT_BLOCK55(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK55_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK55_MASK) 739 740 #define MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK (0x1000000U) 741 #define MC_ME_PRTN1_COFB1_STAT_BLOCK56_SHIFT (24U) 742 #define MC_ME_PRTN1_COFB1_STAT_BLOCK56_WIDTH (1U) 743 #define MC_ME_PRTN1_COFB1_STAT_BLOCK56(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK56_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) 744 745 #define MC_ME_PRTN1_COFB1_STAT_BLOCK58_MASK (0x4000000U) 746 #define MC_ME_PRTN1_COFB1_STAT_BLOCK58_SHIFT (26U) 747 #define MC_ME_PRTN1_COFB1_STAT_BLOCK58_WIDTH (1U) 748 #define MC_ME_PRTN1_COFB1_STAT_BLOCK58(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK58_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK58_MASK) 749 750 #define MC_ME_PRTN1_COFB1_STAT_BLOCK59_MASK (0x8000000U) 751 #define MC_ME_PRTN1_COFB1_STAT_BLOCK59_SHIFT (27U) 752 #define MC_ME_PRTN1_COFB1_STAT_BLOCK59_WIDTH (1U) 753 #define MC_ME_PRTN1_COFB1_STAT_BLOCK59(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK59_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK59_MASK) 754 755 #define MC_ME_PRTN1_COFB1_STAT_BLOCK60_MASK (0x10000000U) 756 #define MC_ME_PRTN1_COFB1_STAT_BLOCK60_SHIFT (28U) 757 #define MC_ME_PRTN1_COFB1_STAT_BLOCK60_WIDTH (1U) 758 #define MC_ME_PRTN1_COFB1_STAT_BLOCK60(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK60_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK60_MASK) 759 760 #define MC_ME_PRTN1_COFB1_STAT_BLOCK63_MASK (0x80000000U) 761 #define MC_ME_PRTN1_COFB1_STAT_BLOCK63_SHIFT (31U) 762 #define MC_ME_PRTN1_COFB1_STAT_BLOCK63_WIDTH (1U) 763 #define MC_ME_PRTN1_COFB1_STAT_BLOCK63(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_STAT_BLOCK63_SHIFT)) & MC_ME_PRTN1_COFB1_STAT_BLOCK63_MASK) 764 /*! @} */ 765 766 /*! @name PRTN1_COFB2_STAT - Partition 1 COFB Set 2 Clock Status Register */ 767 /*! @{ */ 768 769 #define MC_ME_PRTN1_COFB2_STAT_BLOCK65_MASK (0x2U) 770 #define MC_ME_PRTN1_COFB2_STAT_BLOCK65_SHIFT (1U) 771 #define MC_ME_PRTN1_COFB2_STAT_BLOCK65_WIDTH (1U) 772 #define MC_ME_PRTN1_COFB2_STAT_BLOCK65(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK65_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK65_MASK) 773 774 #define MC_ME_PRTN1_COFB2_STAT_BLOCK66_MASK (0x4U) 775 #define MC_ME_PRTN1_COFB2_STAT_BLOCK66_SHIFT (2U) 776 #define MC_ME_PRTN1_COFB2_STAT_BLOCK66_WIDTH (1U) 777 #define MC_ME_PRTN1_COFB2_STAT_BLOCK66(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK66_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK66_MASK) 778 779 #define MC_ME_PRTN1_COFB2_STAT_BLOCK67_MASK (0x8U) 780 #define MC_ME_PRTN1_COFB2_STAT_BLOCK67_SHIFT (3U) 781 #define MC_ME_PRTN1_COFB2_STAT_BLOCK67_WIDTH (1U) 782 #define MC_ME_PRTN1_COFB2_STAT_BLOCK67(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK67_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK67_MASK) 783 784 #define MC_ME_PRTN1_COFB2_STAT_BLOCK68_MASK (0x10U) 785 #define MC_ME_PRTN1_COFB2_STAT_BLOCK68_SHIFT (4U) 786 #define MC_ME_PRTN1_COFB2_STAT_BLOCK68_WIDTH (1U) 787 #define MC_ME_PRTN1_COFB2_STAT_BLOCK68(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK68_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK68_MASK) 788 789 #define MC_ME_PRTN1_COFB2_STAT_BLOCK69_MASK (0x20U) 790 #define MC_ME_PRTN1_COFB2_STAT_BLOCK69_SHIFT (5U) 791 #define MC_ME_PRTN1_COFB2_STAT_BLOCK69_WIDTH (1U) 792 #define MC_ME_PRTN1_COFB2_STAT_BLOCK69(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK69_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK69_MASK) 793 794 #define MC_ME_PRTN1_COFB2_STAT_BLOCK70_MASK (0x40U) 795 #define MC_ME_PRTN1_COFB2_STAT_BLOCK70_SHIFT (6U) 796 #define MC_ME_PRTN1_COFB2_STAT_BLOCK70_WIDTH (1U) 797 #define MC_ME_PRTN1_COFB2_STAT_BLOCK70(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK70_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK70_MASK) 798 799 #define MC_ME_PRTN1_COFB2_STAT_BLOCK73_MASK (0x200U) 800 #define MC_ME_PRTN1_COFB2_STAT_BLOCK73_SHIFT (9U) 801 #define MC_ME_PRTN1_COFB2_STAT_BLOCK73_WIDTH (1U) 802 #define MC_ME_PRTN1_COFB2_STAT_BLOCK73(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK73_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK73_MASK) 803 804 #define MC_ME_PRTN1_COFB2_STAT_BLOCK74_MASK (0x400U) 805 #define MC_ME_PRTN1_COFB2_STAT_BLOCK74_SHIFT (10U) 806 #define MC_ME_PRTN1_COFB2_STAT_BLOCK74_WIDTH (1U) 807 #define MC_ME_PRTN1_COFB2_STAT_BLOCK74(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK74_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK74_MASK) 808 809 #define MC_ME_PRTN1_COFB2_STAT_BLOCK75_MASK (0x800U) 810 #define MC_ME_PRTN1_COFB2_STAT_BLOCK75_SHIFT (11U) 811 #define MC_ME_PRTN1_COFB2_STAT_BLOCK75_WIDTH (1U) 812 #define MC_ME_PRTN1_COFB2_STAT_BLOCK75(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK75_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK75_MASK) 813 814 #define MC_ME_PRTN1_COFB2_STAT_BLOCK76_MASK (0x1000U) 815 #define MC_ME_PRTN1_COFB2_STAT_BLOCK76_SHIFT (12U) 816 #define MC_ME_PRTN1_COFB2_STAT_BLOCK76_WIDTH (1U) 817 #define MC_ME_PRTN1_COFB2_STAT_BLOCK76(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK76_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK76_MASK) 818 819 #define MC_ME_PRTN1_COFB2_STAT_BLOCK77_MASK (0x2000U) 820 #define MC_ME_PRTN1_COFB2_STAT_BLOCK77_SHIFT (13U) 821 #define MC_ME_PRTN1_COFB2_STAT_BLOCK77_WIDTH (1U) 822 #define MC_ME_PRTN1_COFB2_STAT_BLOCK77(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK77_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK77_MASK) 823 824 #define MC_ME_PRTN1_COFB2_STAT_BLOCK78_MASK (0x4000U) 825 #define MC_ME_PRTN1_COFB2_STAT_BLOCK78_SHIFT (14U) 826 #define MC_ME_PRTN1_COFB2_STAT_BLOCK78_WIDTH (1U) 827 #define MC_ME_PRTN1_COFB2_STAT_BLOCK78(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK78_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK78_MASK) 828 829 #define MC_ME_PRTN1_COFB2_STAT_BLOCK79_MASK (0x8000U) 830 #define MC_ME_PRTN1_COFB2_STAT_BLOCK79_SHIFT (15U) 831 #define MC_ME_PRTN1_COFB2_STAT_BLOCK79_WIDTH (1U) 832 #define MC_ME_PRTN1_COFB2_STAT_BLOCK79(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK79_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK79_MASK) 833 834 #define MC_ME_PRTN1_COFB2_STAT_BLOCK80_MASK (0x10000U) 835 #define MC_ME_PRTN1_COFB2_STAT_BLOCK80_SHIFT (16U) 836 #define MC_ME_PRTN1_COFB2_STAT_BLOCK80_WIDTH (1U) 837 #define MC_ME_PRTN1_COFB2_STAT_BLOCK80(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK80_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK80_MASK) 838 839 #define MC_ME_PRTN1_COFB2_STAT_BLOCK81_MASK (0x20000U) 840 #define MC_ME_PRTN1_COFB2_STAT_BLOCK81_SHIFT (17U) 841 #define MC_ME_PRTN1_COFB2_STAT_BLOCK81_WIDTH (1U) 842 #define MC_ME_PRTN1_COFB2_STAT_BLOCK81(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK81_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK81_MASK) 843 844 #define MC_ME_PRTN1_COFB2_STAT_BLOCK84_MASK (0x100000U) 845 #define MC_ME_PRTN1_COFB2_STAT_BLOCK84_SHIFT (20U) 846 #define MC_ME_PRTN1_COFB2_STAT_BLOCK84_WIDTH (1U) 847 #define MC_ME_PRTN1_COFB2_STAT_BLOCK84(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK84_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK84_MASK) 848 849 #define MC_ME_PRTN1_COFB2_STAT_BLOCK85_MASK (0x200000U) 850 #define MC_ME_PRTN1_COFB2_STAT_BLOCK85_SHIFT (21U) 851 #define MC_ME_PRTN1_COFB2_STAT_BLOCK85_WIDTH (1U) 852 #define MC_ME_PRTN1_COFB2_STAT_BLOCK85(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK85_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK85_MASK) 853 854 #define MC_ME_PRTN1_COFB2_STAT_BLOCK86_MASK (0x400000U) 855 #define MC_ME_PRTN1_COFB2_STAT_BLOCK86_SHIFT (22U) 856 #define MC_ME_PRTN1_COFB2_STAT_BLOCK86_WIDTH (1U) 857 #define MC_ME_PRTN1_COFB2_STAT_BLOCK86(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK86_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK86_MASK) 858 859 #define MC_ME_PRTN1_COFB2_STAT_BLOCK87_MASK (0x800000U) 860 #define MC_ME_PRTN1_COFB2_STAT_BLOCK87_SHIFT (23U) 861 #define MC_ME_PRTN1_COFB2_STAT_BLOCK87_WIDTH (1U) 862 #define MC_ME_PRTN1_COFB2_STAT_BLOCK87(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK87_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK87_MASK) 863 864 #define MC_ME_PRTN1_COFB2_STAT_BLOCK88_MASK (0x1000000U) 865 #define MC_ME_PRTN1_COFB2_STAT_BLOCK88_SHIFT (24U) 866 #define MC_ME_PRTN1_COFB2_STAT_BLOCK88_WIDTH (1U) 867 #define MC_ME_PRTN1_COFB2_STAT_BLOCK88(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK88_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK88_MASK) 868 869 #define MC_ME_PRTN1_COFB2_STAT_BLOCK89_MASK (0x2000000U) 870 #define MC_ME_PRTN1_COFB2_STAT_BLOCK89_SHIFT (25U) 871 #define MC_ME_PRTN1_COFB2_STAT_BLOCK89_WIDTH (1U) 872 #define MC_ME_PRTN1_COFB2_STAT_BLOCK89(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK89_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK89_MASK) 873 874 #define MC_ME_PRTN1_COFB2_STAT_BLOCK91_MASK (0x8000000U) 875 #define MC_ME_PRTN1_COFB2_STAT_BLOCK91_SHIFT (27U) 876 #define MC_ME_PRTN1_COFB2_STAT_BLOCK91_WIDTH (1U) 877 #define MC_ME_PRTN1_COFB2_STAT_BLOCK91(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK91_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK91_MASK) 878 879 #define MC_ME_PRTN1_COFB2_STAT_BLOCK92_MASK (0x10000000U) 880 #define MC_ME_PRTN1_COFB2_STAT_BLOCK92_SHIFT (28U) 881 #define MC_ME_PRTN1_COFB2_STAT_BLOCK92_WIDTH (1U) 882 #define MC_ME_PRTN1_COFB2_STAT_BLOCK92(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK92_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK92_MASK) 883 884 #define MC_ME_PRTN1_COFB2_STAT_BLOCK93_MASK (0x20000000U) 885 #define MC_ME_PRTN1_COFB2_STAT_BLOCK93_SHIFT (29U) 886 #define MC_ME_PRTN1_COFB2_STAT_BLOCK93_WIDTH (1U) 887 #define MC_ME_PRTN1_COFB2_STAT_BLOCK93(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK93_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK93_MASK) 888 889 #define MC_ME_PRTN1_COFB2_STAT_BLOCK95_MASK (0x80000000U) 890 #define MC_ME_PRTN1_COFB2_STAT_BLOCK95_SHIFT (31U) 891 #define MC_ME_PRTN1_COFB2_STAT_BLOCK95_WIDTH (1U) 892 #define MC_ME_PRTN1_COFB2_STAT_BLOCK95(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_STAT_BLOCK95_SHIFT)) & MC_ME_PRTN1_COFB2_STAT_BLOCK95_MASK) 893 /*! @} */ 894 895 /*! @name PRTN1_COFB3_STAT - Partition 1 COFB Set 3 Clock Status Register */ 896 /*! @{ */ 897 898 #define MC_ME_PRTN1_COFB3_STAT_BLOCK96_MASK (0x1U) 899 #define MC_ME_PRTN1_COFB3_STAT_BLOCK96_SHIFT (0U) 900 #define MC_ME_PRTN1_COFB3_STAT_BLOCK96_WIDTH (1U) 901 #define MC_ME_PRTN1_COFB3_STAT_BLOCK96(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK96_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK96_MASK) 902 903 #define MC_ME_PRTN1_COFB3_STAT_BLOCK97_MASK (0x2U) 904 #define MC_ME_PRTN1_COFB3_STAT_BLOCK97_SHIFT (1U) 905 #define MC_ME_PRTN1_COFB3_STAT_BLOCK97_WIDTH (1U) 906 #define MC_ME_PRTN1_COFB3_STAT_BLOCK97(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK97_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK97_MASK) 907 908 #define MC_ME_PRTN1_COFB3_STAT_BLOCK98_MASK (0x4U) 909 #define MC_ME_PRTN1_COFB3_STAT_BLOCK98_SHIFT (2U) 910 #define MC_ME_PRTN1_COFB3_STAT_BLOCK98_WIDTH (1U) 911 #define MC_ME_PRTN1_COFB3_STAT_BLOCK98(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK98_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK98_MASK) 912 913 #define MC_ME_PRTN1_COFB3_STAT_BLOCK99_MASK (0x8U) 914 #define MC_ME_PRTN1_COFB3_STAT_BLOCK99_SHIFT (3U) 915 #define MC_ME_PRTN1_COFB3_STAT_BLOCK99_WIDTH (1U) 916 #define MC_ME_PRTN1_COFB3_STAT_BLOCK99(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK99_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK99_MASK) 917 918 #define MC_ME_PRTN1_COFB3_STAT_BLOCK101_MASK (0x20U) 919 #define MC_ME_PRTN1_COFB3_STAT_BLOCK101_SHIFT (5U) 920 #define MC_ME_PRTN1_COFB3_STAT_BLOCK101_WIDTH (1U) 921 #define MC_ME_PRTN1_COFB3_STAT_BLOCK101(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK101_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK101_MASK) 922 923 #define MC_ME_PRTN1_COFB3_STAT_BLOCK102_MASK (0x40U) 924 #define MC_ME_PRTN1_COFB3_STAT_BLOCK102_SHIFT (6U) 925 #define MC_ME_PRTN1_COFB3_STAT_BLOCK102_WIDTH (1U) 926 #define MC_ME_PRTN1_COFB3_STAT_BLOCK102(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK102_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK102_MASK) 927 928 #define MC_ME_PRTN1_COFB3_STAT_BLOCK103_MASK (0x80U) 929 #define MC_ME_PRTN1_COFB3_STAT_BLOCK103_SHIFT (7U) 930 #define MC_ME_PRTN1_COFB3_STAT_BLOCK103_WIDTH (1U) 931 #define MC_ME_PRTN1_COFB3_STAT_BLOCK103(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK103_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK103_MASK) 932 933 #define MC_ME_PRTN1_COFB3_STAT_BLOCK104_MASK (0x100U) 934 #define MC_ME_PRTN1_COFB3_STAT_BLOCK104_SHIFT (8U) 935 #define MC_ME_PRTN1_COFB3_STAT_BLOCK104_WIDTH (1U) 936 #define MC_ME_PRTN1_COFB3_STAT_BLOCK104(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK104_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK104_MASK) 937 938 #define MC_ME_PRTN1_COFB3_STAT_BLOCK105_MASK (0x200U) 939 #define MC_ME_PRTN1_COFB3_STAT_BLOCK105_SHIFT (9U) 940 #define MC_ME_PRTN1_COFB3_STAT_BLOCK105_WIDTH (1U) 941 #define MC_ME_PRTN1_COFB3_STAT_BLOCK105(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK105_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK105_MASK) 942 943 #define MC_ME_PRTN1_COFB3_STAT_BLOCK106_MASK (0x400U) 944 #define MC_ME_PRTN1_COFB3_STAT_BLOCK106_SHIFT (10U) 945 #define MC_ME_PRTN1_COFB3_STAT_BLOCK106_WIDTH (1U) 946 #define MC_ME_PRTN1_COFB3_STAT_BLOCK106(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK106_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK106_MASK) 947 948 #define MC_ME_PRTN1_COFB3_STAT_BLOCK107_MASK (0x800U) 949 #define MC_ME_PRTN1_COFB3_STAT_BLOCK107_SHIFT (11U) 950 #define MC_ME_PRTN1_COFB3_STAT_BLOCK107_WIDTH (1U) 951 #define MC_ME_PRTN1_COFB3_STAT_BLOCK107(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK107_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK107_MASK) 952 953 #define MC_ME_PRTN1_COFB3_STAT_BLOCK108_MASK (0x1000U) 954 #define MC_ME_PRTN1_COFB3_STAT_BLOCK108_SHIFT (12U) 955 #define MC_ME_PRTN1_COFB3_STAT_BLOCK108_WIDTH (1U) 956 #define MC_ME_PRTN1_COFB3_STAT_BLOCK108(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK108_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK108_MASK) 957 958 #define MC_ME_PRTN1_COFB3_STAT_BLOCK110_MASK (0x4000U) 959 #define MC_ME_PRTN1_COFB3_STAT_BLOCK110_SHIFT (14U) 960 #define MC_ME_PRTN1_COFB3_STAT_BLOCK110_WIDTH (1U) 961 #define MC_ME_PRTN1_COFB3_STAT_BLOCK110(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_STAT_BLOCK110_SHIFT)) & MC_ME_PRTN1_COFB3_STAT_BLOCK110_MASK) 962 /*! @} */ 963 964 /*! @name PRTN1_COFB0_CLKEN - Partition 1 COFB Set 0 Clock Enable Register */ 965 /*! @{ */ 966 967 #define MC_ME_PRTN1_COFB0_CLKEN_REQ3_MASK (0x8U) 968 #define MC_ME_PRTN1_COFB0_CLKEN_REQ3_SHIFT (3U) 969 #define MC_ME_PRTN1_COFB0_CLKEN_REQ3_WIDTH (1U) 970 #define MC_ME_PRTN1_COFB0_CLKEN_REQ3(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ3_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ3_MASK) 971 972 #define MC_ME_PRTN1_COFB0_CLKEN_REQ4_MASK (0x10U) 973 #define MC_ME_PRTN1_COFB0_CLKEN_REQ4_SHIFT (4U) 974 #define MC_ME_PRTN1_COFB0_CLKEN_REQ4_WIDTH (1U) 975 #define MC_ME_PRTN1_COFB0_CLKEN_REQ4(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ4_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ4_MASK) 976 977 #define MC_ME_PRTN1_COFB0_CLKEN_REQ5_MASK (0x20U) 978 #define MC_ME_PRTN1_COFB0_CLKEN_REQ5_SHIFT (5U) 979 #define MC_ME_PRTN1_COFB0_CLKEN_REQ5_WIDTH (1U) 980 #define MC_ME_PRTN1_COFB0_CLKEN_REQ5(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ5_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ5_MASK) 981 982 #define MC_ME_PRTN1_COFB0_CLKEN_REQ6_MASK (0x40U) 983 #define MC_ME_PRTN1_COFB0_CLKEN_REQ6_SHIFT (6U) 984 #define MC_ME_PRTN1_COFB0_CLKEN_REQ6_WIDTH (1U) 985 #define MC_ME_PRTN1_COFB0_CLKEN_REQ6(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ6_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ6_MASK) 986 987 #define MC_ME_PRTN1_COFB0_CLKEN_REQ7_MASK (0x80U) 988 #define MC_ME_PRTN1_COFB0_CLKEN_REQ7_SHIFT (7U) 989 #define MC_ME_PRTN1_COFB0_CLKEN_REQ7_WIDTH (1U) 990 #define MC_ME_PRTN1_COFB0_CLKEN_REQ7(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ7_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ7_MASK) 991 992 #define MC_ME_PRTN1_COFB0_CLKEN_REQ8_MASK (0x100U) 993 #define MC_ME_PRTN1_COFB0_CLKEN_REQ8_SHIFT (8U) 994 #define MC_ME_PRTN1_COFB0_CLKEN_REQ8_WIDTH (1U) 995 #define MC_ME_PRTN1_COFB0_CLKEN_REQ8(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ8_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ8_MASK) 996 997 #define MC_ME_PRTN1_COFB0_CLKEN_REQ9_MASK (0x200U) 998 #define MC_ME_PRTN1_COFB0_CLKEN_REQ9_SHIFT (9U) 999 #define MC_ME_PRTN1_COFB0_CLKEN_REQ9_WIDTH (1U) 1000 #define MC_ME_PRTN1_COFB0_CLKEN_REQ9(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ9_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ9_MASK) 1001 1002 #define MC_ME_PRTN1_COFB0_CLKEN_REQ10_MASK (0x400U) 1003 #define MC_ME_PRTN1_COFB0_CLKEN_REQ10_SHIFT (10U) 1004 #define MC_ME_PRTN1_COFB0_CLKEN_REQ10_WIDTH (1U) 1005 #define MC_ME_PRTN1_COFB0_CLKEN_REQ10(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ10_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ10_MASK) 1006 1007 #define MC_ME_PRTN1_COFB0_CLKEN_REQ11_MASK (0x800U) 1008 #define MC_ME_PRTN1_COFB0_CLKEN_REQ11_SHIFT (11U) 1009 #define MC_ME_PRTN1_COFB0_CLKEN_REQ11_WIDTH (1U) 1010 #define MC_ME_PRTN1_COFB0_CLKEN_REQ11(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ11_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ11_MASK) 1011 1012 #define MC_ME_PRTN1_COFB0_CLKEN_REQ12_MASK (0x1000U) 1013 #define MC_ME_PRTN1_COFB0_CLKEN_REQ12_SHIFT (12U) 1014 #define MC_ME_PRTN1_COFB0_CLKEN_REQ12_WIDTH (1U) 1015 #define MC_ME_PRTN1_COFB0_CLKEN_REQ12(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ12_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ12_MASK) 1016 1017 #define MC_ME_PRTN1_COFB0_CLKEN_REQ13_MASK (0x2000U) 1018 #define MC_ME_PRTN1_COFB0_CLKEN_REQ13_SHIFT (13U) 1019 #define MC_ME_PRTN1_COFB0_CLKEN_REQ13_WIDTH (1U) 1020 #define MC_ME_PRTN1_COFB0_CLKEN_REQ13(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ13_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ13_MASK) 1021 1022 #define MC_ME_PRTN1_COFB0_CLKEN_REQ14_MASK (0x4000U) 1023 #define MC_ME_PRTN1_COFB0_CLKEN_REQ14_SHIFT (14U) 1024 #define MC_ME_PRTN1_COFB0_CLKEN_REQ14_WIDTH (1U) 1025 #define MC_ME_PRTN1_COFB0_CLKEN_REQ14(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ14_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ14_MASK) 1026 1027 #define MC_ME_PRTN1_COFB0_CLKEN_REQ15_MASK (0x8000U) 1028 #define MC_ME_PRTN1_COFB0_CLKEN_REQ15_SHIFT (15U) 1029 #define MC_ME_PRTN1_COFB0_CLKEN_REQ15_WIDTH (1U) 1030 #define MC_ME_PRTN1_COFB0_CLKEN_REQ15(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ15_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ15_MASK) 1031 1032 #define MC_ME_PRTN1_COFB0_CLKEN_REQ21_MASK (0x200000U) 1033 #define MC_ME_PRTN1_COFB0_CLKEN_REQ21_SHIFT (21U) 1034 #define MC_ME_PRTN1_COFB0_CLKEN_REQ21_WIDTH (1U) 1035 #define MC_ME_PRTN1_COFB0_CLKEN_REQ21(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ21_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ21_MASK) 1036 1037 #define MC_ME_PRTN1_COFB0_CLKEN_REQ22_MASK (0x400000U) 1038 #define MC_ME_PRTN1_COFB0_CLKEN_REQ22_SHIFT (22U) 1039 #define MC_ME_PRTN1_COFB0_CLKEN_REQ22_WIDTH (1U) 1040 #define MC_ME_PRTN1_COFB0_CLKEN_REQ22(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ22_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ22_MASK) 1041 1042 #define MC_ME_PRTN1_COFB0_CLKEN_REQ23_MASK (0x800000U) 1043 #define MC_ME_PRTN1_COFB0_CLKEN_REQ23_SHIFT (23U) 1044 #define MC_ME_PRTN1_COFB0_CLKEN_REQ23_WIDTH (1U) 1045 #define MC_ME_PRTN1_COFB0_CLKEN_REQ23(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ23_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ23_MASK) 1046 1047 #define MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK (0x1000000U) 1048 #define MC_ME_PRTN1_COFB0_CLKEN_REQ24_SHIFT (24U) 1049 #define MC_ME_PRTN1_COFB0_CLKEN_REQ24_WIDTH (1U) 1050 #define MC_ME_PRTN1_COFB0_CLKEN_REQ24(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ24_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK) 1051 1052 #define MC_ME_PRTN1_COFB0_CLKEN_REQ28_MASK (0x10000000U) 1053 #define MC_ME_PRTN1_COFB0_CLKEN_REQ28_SHIFT (28U) 1054 #define MC_ME_PRTN1_COFB0_CLKEN_REQ28_WIDTH (1U) 1055 #define MC_ME_PRTN1_COFB0_CLKEN_REQ28(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ28_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ28_MASK) 1056 1057 #define MC_ME_PRTN1_COFB0_CLKEN_REQ29_MASK (0x20000000U) 1058 #define MC_ME_PRTN1_COFB0_CLKEN_REQ29_SHIFT (29U) 1059 #define MC_ME_PRTN1_COFB0_CLKEN_REQ29_WIDTH (1U) 1060 #define MC_ME_PRTN1_COFB0_CLKEN_REQ29(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ29_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ29_MASK) 1061 1062 #define MC_ME_PRTN1_COFB0_CLKEN_REQ31_MASK (0x80000000U) 1063 #define MC_ME_PRTN1_COFB0_CLKEN_REQ31_SHIFT (31U) 1064 #define MC_ME_PRTN1_COFB0_CLKEN_REQ31_WIDTH (1U) 1065 #define MC_ME_PRTN1_COFB0_CLKEN_REQ31(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB0_CLKEN_REQ31_SHIFT)) & MC_ME_PRTN1_COFB0_CLKEN_REQ31_MASK) 1066 /*! @} */ 1067 1068 /*! @name PRTN1_COFB1_CLKEN - Partition 1 COFB Set 1 Clock Enable Register */ 1069 /*! @{ */ 1070 1071 #define MC_ME_PRTN1_COFB1_CLKEN_REQ32_MASK (0x1U) 1072 #define MC_ME_PRTN1_COFB1_CLKEN_REQ32_SHIFT (0U) 1073 #define MC_ME_PRTN1_COFB1_CLKEN_REQ32_WIDTH (1U) 1074 #define MC_ME_PRTN1_COFB1_CLKEN_REQ32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ32_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ32_MASK) 1075 1076 #define MC_ME_PRTN1_COFB1_CLKEN_REQ33_MASK (0x2U) 1077 #define MC_ME_PRTN1_COFB1_CLKEN_REQ33_SHIFT (1U) 1078 #define MC_ME_PRTN1_COFB1_CLKEN_REQ33_WIDTH (1U) 1079 #define MC_ME_PRTN1_COFB1_CLKEN_REQ33(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ33_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ33_MASK) 1080 1081 #define MC_ME_PRTN1_COFB1_CLKEN_REQ34_MASK (0x4U) 1082 #define MC_ME_PRTN1_COFB1_CLKEN_REQ34_SHIFT (2U) 1083 #define MC_ME_PRTN1_COFB1_CLKEN_REQ34_WIDTH (1U) 1084 #define MC_ME_PRTN1_COFB1_CLKEN_REQ34(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ34_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ34_MASK) 1085 1086 #define MC_ME_PRTN1_COFB1_CLKEN_REQ42_MASK (0x400U) 1087 #define MC_ME_PRTN1_COFB1_CLKEN_REQ42_SHIFT (10U) 1088 #define MC_ME_PRTN1_COFB1_CLKEN_REQ42_WIDTH (1U) 1089 #define MC_ME_PRTN1_COFB1_CLKEN_REQ42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ42_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ42_MASK) 1090 1091 #define MC_ME_PRTN1_COFB1_CLKEN_REQ45_MASK (0x2000U) 1092 #define MC_ME_PRTN1_COFB1_CLKEN_REQ45_SHIFT (13U) 1093 #define MC_ME_PRTN1_COFB1_CLKEN_REQ45_WIDTH (1U) 1094 #define MC_ME_PRTN1_COFB1_CLKEN_REQ45(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ45_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ45_MASK) 1095 1096 #define MC_ME_PRTN1_COFB1_CLKEN_REQ47_MASK (0x8000U) 1097 #define MC_ME_PRTN1_COFB1_CLKEN_REQ47_SHIFT (15U) 1098 #define MC_ME_PRTN1_COFB1_CLKEN_REQ47_WIDTH (1U) 1099 #define MC_ME_PRTN1_COFB1_CLKEN_REQ47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ47_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ47_MASK) 1100 1101 #define MC_ME_PRTN1_COFB1_CLKEN_REQ49_MASK (0x20000U) 1102 #define MC_ME_PRTN1_COFB1_CLKEN_REQ49_SHIFT (17U) 1103 #define MC_ME_PRTN1_COFB1_CLKEN_REQ49_WIDTH (1U) 1104 #define MC_ME_PRTN1_COFB1_CLKEN_REQ49(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ49_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ49_MASK) 1105 1106 #define MC_ME_PRTN1_COFB1_CLKEN_REQ51_MASK (0x80000U) 1107 #define MC_ME_PRTN1_COFB1_CLKEN_REQ51_SHIFT (19U) 1108 #define MC_ME_PRTN1_COFB1_CLKEN_REQ51_WIDTH (1U) 1109 #define MC_ME_PRTN1_COFB1_CLKEN_REQ51(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ51_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ51_MASK) 1110 1111 #define MC_ME_PRTN1_COFB1_CLKEN_REQ53_MASK (0x200000U) 1112 #define MC_ME_PRTN1_COFB1_CLKEN_REQ53_SHIFT (21U) 1113 #define MC_ME_PRTN1_COFB1_CLKEN_REQ53_WIDTH (1U) 1114 #define MC_ME_PRTN1_COFB1_CLKEN_REQ53(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ53_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ53_MASK) 1115 1116 #define MC_ME_PRTN1_COFB1_CLKEN_REQ56_MASK (0x1000000U) 1117 #define MC_ME_PRTN1_COFB1_CLKEN_REQ56_SHIFT (24U) 1118 #define MC_ME_PRTN1_COFB1_CLKEN_REQ56_WIDTH (1U) 1119 #define MC_ME_PRTN1_COFB1_CLKEN_REQ56(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ56_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ56_MASK) 1120 1121 #define MC_ME_PRTN1_COFB1_CLKEN_REQ63_MASK (0x80000000U) 1122 #define MC_ME_PRTN1_COFB1_CLKEN_REQ63_SHIFT (31U) 1123 #define MC_ME_PRTN1_COFB1_CLKEN_REQ63_WIDTH (1U) 1124 #define MC_ME_PRTN1_COFB1_CLKEN_REQ63(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB1_CLKEN_REQ63_SHIFT)) & MC_ME_PRTN1_COFB1_CLKEN_REQ63_MASK) 1125 /*! @} */ 1126 1127 /*! @name PRTN1_COFB2_CLKEN - Partition 1 COFB Set 2 Clock Enable Register */ 1128 /*! @{ */ 1129 1130 #define MC_ME_PRTN1_COFB2_CLKEN_REQ65_MASK (0x2U) 1131 #define MC_ME_PRTN1_COFB2_CLKEN_REQ65_SHIFT (1U) 1132 #define MC_ME_PRTN1_COFB2_CLKEN_REQ65_WIDTH (1U) 1133 #define MC_ME_PRTN1_COFB2_CLKEN_REQ65(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ65_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ65_MASK) 1134 1135 #define MC_ME_PRTN1_COFB2_CLKEN_REQ66_MASK (0x4U) 1136 #define MC_ME_PRTN1_COFB2_CLKEN_REQ66_SHIFT (2U) 1137 #define MC_ME_PRTN1_COFB2_CLKEN_REQ66_WIDTH (1U) 1138 #define MC_ME_PRTN1_COFB2_CLKEN_REQ66(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ66_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ66_MASK) 1139 1140 #define MC_ME_PRTN1_COFB2_CLKEN_REQ67_MASK (0x8U) 1141 #define MC_ME_PRTN1_COFB2_CLKEN_REQ67_SHIFT (3U) 1142 #define MC_ME_PRTN1_COFB2_CLKEN_REQ67_WIDTH (1U) 1143 #define MC_ME_PRTN1_COFB2_CLKEN_REQ67(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ67_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ67_MASK) 1144 1145 #define MC_ME_PRTN1_COFB2_CLKEN_REQ68_MASK (0x10U) 1146 #define MC_ME_PRTN1_COFB2_CLKEN_REQ68_SHIFT (4U) 1147 #define MC_ME_PRTN1_COFB2_CLKEN_REQ68_WIDTH (1U) 1148 #define MC_ME_PRTN1_COFB2_CLKEN_REQ68(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ68_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ68_MASK) 1149 1150 #define MC_ME_PRTN1_COFB2_CLKEN_REQ69_MASK (0x20U) 1151 #define MC_ME_PRTN1_COFB2_CLKEN_REQ69_SHIFT (5U) 1152 #define MC_ME_PRTN1_COFB2_CLKEN_REQ69_WIDTH (1U) 1153 #define MC_ME_PRTN1_COFB2_CLKEN_REQ69(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ69_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ69_MASK) 1154 1155 #define MC_ME_PRTN1_COFB2_CLKEN_REQ70_MASK (0x40U) 1156 #define MC_ME_PRTN1_COFB2_CLKEN_REQ70_SHIFT (6U) 1157 #define MC_ME_PRTN1_COFB2_CLKEN_REQ70_WIDTH (1U) 1158 #define MC_ME_PRTN1_COFB2_CLKEN_REQ70(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ70_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ70_MASK) 1159 1160 #define MC_ME_PRTN1_COFB2_CLKEN_REQ73_MASK (0x200U) 1161 #define MC_ME_PRTN1_COFB2_CLKEN_REQ73_SHIFT (9U) 1162 #define MC_ME_PRTN1_COFB2_CLKEN_REQ73_WIDTH (1U) 1163 #define MC_ME_PRTN1_COFB2_CLKEN_REQ73(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ73_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ73_MASK) 1164 1165 #define MC_ME_PRTN1_COFB2_CLKEN_REQ74_MASK (0x400U) 1166 #define MC_ME_PRTN1_COFB2_CLKEN_REQ74_SHIFT (10U) 1167 #define MC_ME_PRTN1_COFB2_CLKEN_REQ74_WIDTH (1U) 1168 #define MC_ME_PRTN1_COFB2_CLKEN_REQ74(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ74_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ74_MASK) 1169 1170 #define MC_ME_PRTN1_COFB2_CLKEN_REQ75_MASK (0x800U) 1171 #define MC_ME_PRTN1_COFB2_CLKEN_REQ75_SHIFT (11U) 1172 #define MC_ME_PRTN1_COFB2_CLKEN_REQ75_WIDTH (1U) 1173 #define MC_ME_PRTN1_COFB2_CLKEN_REQ75(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ75_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ75_MASK) 1174 1175 #define MC_ME_PRTN1_COFB2_CLKEN_REQ76_MASK (0x1000U) 1176 #define MC_ME_PRTN1_COFB2_CLKEN_REQ76_SHIFT (12U) 1177 #define MC_ME_PRTN1_COFB2_CLKEN_REQ76_WIDTH (1U) 1178 #define MC_ME_PRTN1_COFB2_CLKEN_REQ76(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ76_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ76_MASK) 1179 1180 #define MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK (0x2000U) 1181 #define MC_ME_PRTN1_COFB2_CLKEN_REQ77_SHIFT (13U) 1182 #define MC_ME_PRTN1_COFB2_CLKEN_REQ77_WIDTH (1U) 1183 #define MC_ME_PRTN1_COFB2_CLKEN_REQ77(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ77_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK) 1184 1185 #define MC_ME_PRTN1_COFB2_CLKEN_REQ78_MASK (0x4000U) 1186 #define MC_ME_PRTN1_COFB2_CLKEN_REQ78_SHIFT (14U) 1187 #define MC_ME_PRTN1_COFB2_CLKEN_REQ78_WIDTH (1U) 1188 #define MC_ME_PRTN1_COFB2_CLKEN_REQ78(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ78_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ78_MASK) 1189 1190 #define MC_ME_PRTN1_COFB2_CLKEN_REQ79_MASK (0x8000U) 1191 #define MC_ME_PRTN1_COFB2_CLKEN_REQ79_SHIFT (15U) 1192 #define MC_ME_PRTN1_COFB2_CLKEN_REQ79_WIDTH (1U) 1193 #define MC_ME_PRTN1_COFB2_CLKEN_REQ79(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ79_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ79_MASK) 1194 1195 #define MC_ME_PRTN1_COFB2_CLKEN_REQ80_MASK (0x10000U) 1196 #define MC_ME_PRTN1_COFB2_CLKEN_REQ80_SHIFT (16U) 1197 #define MC_ME_PRTN1_COFB2_CLKEN_REQ80_WIDTH (1U) 1198 #define MC_ME_PRTN1_COFB2_CLKEN_REQ80(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ80_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ80_MASK) 1199 1200 #define MC_ME_PRTN1_COFB2_CLKEN_REQ81_MASK (0x20000U) 1201 #define MC_ME_PRTN1_COFB2_CLKEN_REQ81_SHIFT (17U) 1202 #define MC_ME_PRTN1_COFB2_CLKEN_REQ81_WIDTH (1U) 1203 #define MC_ME_PRTN1_COFB2_CLKEN_REQ81(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ81_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ81_MASK) 1204 1205 #define MC_ME_PRTN1_COFB2_CLKEN_REQ84_MASK (0x100000U) 1206 #define MC_ME_PRTN1_COFB2_CLKEN_REQ84_SHIFT (20U) 1207 #define MC_ME_PRTN1_COFB2_CLKEN_REQ84_WIDTH (1U) 1208 #define MC_ME_PRTN1_COFB2_CLKEN_REQ84(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ84_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ84_MASK) 1209 1210 #define MC_ME_PRTN1_COFB2_CLKEN_REQ85_MASK (0x200000U) 1211 #define MC_ME_PRTN1_COFB2_CLKEN_REQ85_SHIFT (21U) 1212 #define MC_ME_PRTN1_COFB2_CLKEN_REQ85_WIDTH (1U) 1213 #define MC_ME_PRTN1_COFB2_CLKEN_REQ85(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ85_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ85_MASK) 1214 1215 #define MC_ME_PRTN1_COFB2_CLKEN_REQ86_MASK (0x400000U) 1216 #define MC_ME_PRTN1_COFB2_CLKEN_REQ86_SHIFT (22U) 1217 #define MC_ME_PRTN1_COFB2_CLKEN_REQ86_WIDTH (1U) 1218 #define MC_ME_PRTN1_COFB2_CLKEN_REQ86(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ86_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ86_MASK) 1219 1220 #define MC_ME_PRTN1_COFB2_CLKEN_REQ87_MASK (0x800000U) 1221 #define MC_ME_PRTN1_COFB2_CLKEN_REQ87_SHIFT (23U) 1222 #define MC_ME_PRTN1_COFB2_CLKEN_REQ87_WIDTH (1U) 1223 #define MC_ME_PRTN1_COFB2_CLKEN_REQ87(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ87_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ87_MASK) 1224 1225 #define MC_ME_PRTN1_COFB2_CLKEN_REQ88_MASK (0x1000000U) 1226 #define MC_ME_PRTN1_COFB2_CLKEN_REQ88_SHIFT (24U) 1227 #define MC_ME_PRTN1_COFB2_CLKEN_REQ88_WIDTH (1U) 1228 #define MC_ME_PRTN1_COFB2_CLKEN_REQ88(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ88_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ88_MASK) 1229 1230 #define MC_ME_PRTN1_COFB2_CLKEN_REQ89_MASK (0x2000000U) 1231 #define MC_ME_PRTN1_COFB2_CLKEN_REQ89_SHIFT (25U) 1232 #define MC_ME_PRTN1_COFB2_CLKEN_REQ89_WIDTH (1U) 1233 #define MC_ME_PRTN1_COFB2_CLKEN_REQ89(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ89_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ89_MASK) 1234 1235 #define MC_ME_PRTN1_COFB2_CLKEN_REQ91_MASK (0x8000000U) 1236 #define MC_ME_PRTN1_COFB2_CLKEN_REQ91_SHIFT (27U) 1237 #define MC_ME_PRTN1_COFB2_CLKEN_REQ91_WIDTH (1U) 1238 #define MC_ME_PRTN1_COFB2_CLKEN_REQ91(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ91_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ91_MASK) 1239 1240 #define MC_ME_PRTN1_COFB2_CLKEN_REQ92_MASK (0x10000000U) 1241 #define MC_ME_PRTN1_COFB2_CLKEN_REQ92_SHIFT (28U) 1242 #define MC_ME_PRTN1_COFB2_CLKEN_REQ92_WIDTH (1U) 1243 #define MC_ME_PRTN1_COFB2_CLKEN_REQ92(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ92_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ92_MASK) 1244 1245 #define MC_ME_PRTN1_COFB2_CLKEN_REQ93_MASK (0x20000000U) 1246 #define MC_ME_PRTN1_COFB2_CLKEN_REQ93_SHIFT (29U) 1247 #define MC_ME_PRTN1_COFB2_CLKEN_REQ93_WIDTH (1U) 1248 #define MC_ME_PRTN1_COFB2_CLKEN_REQ93(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ93_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ93_MASK) 1249 1250 #define MC_ME_PRTN1_COFB2_CLKEN_REQ95_MASK (0x80000000U) 1251 #define MC_ME_PRTN1_COFB2_CLKEN_REQ95_SHIFT (31U) 1252 #define MC_ME_PRTN1_COFB2_CLKEN_REQ95_WIDTH (1U) 1253 #define MC_ME_PRTN1_COFB2_CLKEN_REQ95(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB2_CLKEN_REQ95_SHIFT)) & MC_ME_PRTN1_COFB2_CLKEN_REQ95_MASK) 1254 /*! @} */ 1255 1256 /*! @name PRTN1_COFB3_CLKEN - Partition 1 COFB Set 3 Clock Enable Register */ 1257 /*! @{ */ 1258 1259 #define MC_ME_PRTN1_COFB3_CLKEN_REQ96_MASK (0x1U) 1260 #define MC_ME_PRTN1_COFB3_CLKEN_REQ96_SHIFT (0U) 1261 #define MC_ME_PRTN1_COFB3_CLKEN_REQ96_WIDTH (1U) 1262 #define MC_ME_PRTN1_COFB3_CLKEN_REQ96(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_CLKEN_REQ96_SHIFT)) & MC_ME_PRTN1_COFB3_CLKEN_REQ96_MASK) 1263 1264 #define MC_ME_PRTN1_COFB3_CLKEN_REQ102_MASK (0x40U) 1265 #define MC_ME_PRTN1_COFB3_CLKEN_REQ102_SHIFT (6U) 1266 #define MC_ME_PRTN1_COFB3_CLKEN_REQ102_WIDTH (1U) 1267 #define MC_ME_PRTN1_COFB3_CLKEN_REQ102(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_CLKEN_REQ102_SHIFT)) & MC_ME_PRTN1_COFB3_CLKEN_REQ102_MASK) 1268 1269 #define MC_ME_PRTN1_COFB3_CLKEN_REQ104_MASK (0x100U) 1270 #define MC_ME_PRTN1_COFB3_CLKEN_REQ104_SHIFT (8U) 1271 #define MC_ME_PRTN1_COFB3_CLKEN_REQ104_WIDTH (1U) 1272 #define MC_ME_PRTN1_COFB3_CLKEN_REQ104(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN1_COFB3_CLKEN_REQ104_SHIFT)) & MC_ME_PRTN1_COFB3_CLKEN_REQ104_MASK) 1273 /*! @} */ 1274 1275 /*! @name PRTN2_PCONF - Partition 2 Process Configuration Register */ 1276 /*! @{ */ 1277 1278 #define MC_ME_PRTN2_PCONF_PCE_MASK (0x1U) 1279 #define MC_ME_PRTN2_PCONF_PCE_SHIFT (0U) 1280 #define MC_ME_PRTN2_PCONF_PCE_WIDTH (1U) 1281 #define MC_ME_PRTN2_PCONF_PCE(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PCONF_PCE_SHIFT)) & MC_ME_PRTN2_PCONF_PCE_MASK) 1282 /*! @} */ 1283 1284 /*! @name PRTN2_PUPD - Partition 2 Process Update Register */ 1285 /*! @{ */ 1286 1287 #define MC_ME_PRTN2_PUPD_PCUD_MASK (0x1U) 1288 #define MC_ME_PRTN2_PUPD_PCUD_SHIFT (0U) 1289 #define MC_ME_PRTN2_PUPD_PCUD_WIDTH (1U) 1290 #define MC_ME_PRTN2_PUPD_PCUD(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_PUPD_PCUD_SHIFT)) & MC_ME_PRTN2_PUPD_PCUD_MASK) 1291 /*! @} */ 1292 1293 /*! @name PRTN2_STAT - Partition 2 Status Register */ 1294 /*! @{ */ 1295 1296 #define MC_ME_PRTN2_STAT_PCS_MASK (0x1U) 1297 #define MC_ME_PRTN2_STAT_PCS_SHIFT (0U) 1298 #define MC_ME_PRTN2_STAT_PCS_WIDTH (1U) 1299 #define MC_ME_PRTN2_STAT_PCS(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_STAT_PCS_SHIFT)) & MC_ME_PRTN2_STAT_PCS_MASK) 1300 /*! @} */ 1301 1302 /*! @name PRTN2_COFB0_STAT - Partition 2 COFB Set 0 Clock Status Register */ 1303 /*! @{ */ 1304 1305 #define MC_ME_PRTN2_COFB0_STAT_BLOCK0_MASK (0x1U) 1306 #define MC_ME_PRTN2_COFB0_STAT_BLOCK0_SHIFT (0U) 1307 #define MC_ME_PRTN2_COFB0_STAT_BLOCK0_WIDTH (1U) 1308 #define MC_ME_PRTN2_COFB0_STAT_BLOCK0(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK0_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK0_MASK) 1309 1310 #define MC_ME_PRTN2_COFB0_STAT_BLOCK1_MASK (0x2U) 1311 #define MC_ME_PRTN2_COFB0_STAT_BLOCK1_SHIFT (1U) 1312 #define MC_ME_PRTN2_COFB0_STAT_BLOCK1_WIDTH (1U) 1313 #define MC_ME_PRTN2_COFB0_STAT_BLOCK1(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK1_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK1_MASK) 1314 1315 #define MC_ME_PRTN2_COFB0_STAT_BLOCK4_MASK (0x10U) 1316 #define MC_ME_PRTN2_COFB0_STAT_BLOCK4_SHIFT (4U) 1317 #define MC_ME_PRTN2_COFB0_STAT_BLOCK4_WIDTH (1U) 1318 #define MC_ME_PRTN2_COFB0_STAT_BLOCK4(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK4_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK4_MASK) 1319 1320 #define MC_ME_PRTN2_COFB0_STAT_BLOCK5_MASK (0x20U) 1321 #define MC_ME_PRTN2_COFB0_STAT_BLOCK5_SHIFT (5U) 1322 #define MC_ME_PRTN2_COFB0_STAT_BLOCK5_WIDTH (1U) 1323 #define MC_ME_PRTN2_COFB0_STAT_BLOCK5(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK5_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK5_MASK) 1324 1325 #define MC_ME_PRTN2_COFB0_STAT_BLOCK6_MASK (0x40U) 1326 #define MC_ME_PRTN2_COFB0_STAT_BLOCK6_SHIFT (6U) 1327 #define MC_ME_PRTN2_COFB0_STAT_BLOCK6_WIDTH (1U) 1328 #define MC_ME_PRTN2_COFB0_STAT_BLOCK6(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK6_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK6_MASK) 1329 1330 #define MC_ME_PRTN2_COFB0_STAT_BLOCK7_MASK (0x80U) 1331 #define MC_ME_PRTN2_COFB0_STAT_BLOCK7_SHIFT (7U) 1332 #define MC_ME_PRTN2_COFB0_STAT_BLOCK7_WIDTH (1U) 1333 #define MC_ME_PRTN2_COFB0_STAT_BLOCK7(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK7_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK7_MASK) 1334 1335 #define MC_ME_PRTN2_COFB0_STAT_BLOCK8_MASK (0x100U) 1336 #define MC_ME_PRTN2_COFB0_STAT_BLOCK8_SHIFT (8U) 1337 #define MC_ME_PRTN2_COFB0_STAT_BLOCK8_WIDTH (1U) 1338 #define MC_ME_PRTN2_COFB0_STAT_BLOCK8(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK8_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK8_MASK) 1339 1340 #define MC_ME_PRTN2_COFB0_STAT_BLOCK9_MASK (0x200U) 1341 #define MC_ME_PRTN2_COFB0_STAT_BLOCK9_SHIFT (9U) 1342 #define MC_ME_PRTN2_COFB0_STAT_BLOCK9_WIDTH (1U) 1343 #define MC_ME_PRTN2_COFB0_STAT_BLOCK9(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK9_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK9_MASK) 1344 1345 #define MC_ME_PRTN2_COFB0_STAT_BLOCK10_MASK (0x400U) 1346 #define MC_ME_PRTN2_COFB0_STAT_BLOCK10_SHIFT (10U) 1347 #define MC_ME_PRTN2_COFB0_STAT_BLOCK10_WIDTH (1U) 1348 #define MC_ME_PRTN2_COFB0_STAT_BLOCK10(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK10_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK10_MASK) 1349 1350 #define MC_ME_PRTN2_COFB0_STAT_BLOCK11_MASK (0x800U) 1351 #define MC_ME_PRTN2_COFB0_STAT_BLOCK11_SHIFT (11U) 1352 #define MC_ME_PRTN2_COFB0_STAT_BLOCK11_WIDTH (1U) 1353 #define MC_ME_PRTN2_COFB0_STAT_BLOCK11(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK11_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK11_MASK) 1354 1355 #define MC_ME_PRTN2_COFB0_STAT_BLOCK12_MASK (0x1000U) 1356 #define MC_ME_PRTN2_COFB0_STAT_BLOCK12_SHIFT (12U) 1357 #define MC_ME_PRTN2_COFB0_STAT_BLOCK12_WIDTH (1U) 1358 #define MC_ME_PRTN2_COFB0_STAT_BLOCK12(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK12_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK12_MASK) 1359 1360 #define MC_ME_PRTN2_COFB0_STAT_BLOCK13_MASK (0x2000U) 1361 #define MC_ME_PRTN2_COFB0_STAT_BLOCK13_SHIFT (13U) 1362 #define MC_ME_PRTN2_COFB0_STAT_BLOCK13_WIDTH (1U) 1363 #define MC_ME_PRTN2_COFB0_STAT_BLOCK13(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK13_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK13_MASK) 1364 1365 #define MC_ME_PRTN2_COFB0_STAT_BLOCK14_MASK (0x4000U) 1366 #define MC_ME_PRTN2_COFB0_STAT_BLOCK14_SHIFT (14U) 1367 #define MC_ME_PRTN2_COFB0_STAT_BLOCK14_WIDTH (1U) 1368 #define MC_ME_PRTN2_COFB0_STAT_BLOCK14(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK14_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK14_MASK) 1369 1370 #define MC_ME_PRTN2_COFB0_STAT_BLOCK15_MASK (0x8000U) 1371 #define MC_ME_PRTN2_COFB0_STAT_BLOCK15_SHIFT (15U) 1372 #define MC_ME_PRTN2_COFB0_STAT_BLOCK15_WIDTH (1U) 1373 #define MC_ME_PRTN2_COFB0_STAT_BLOCK15(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK15_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK15_MASK) 1374 1375 #define MC_ME_PRTN2_COFB0_STAT_BLOCK16_MASK (0x10000U) 1376 #define MC_ME_PRTN2_COFB0_STAT_BLOCK16_SHIFT (16U) 1377 #define MC_ME_PRTN2_COFB0_STAT_BLOCK16_WIDTH (1U) 1378 #define MC_ME_PRTN2_COFB0_STAT_BLOCK16(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK16_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK16_MASK) 1379 1380 #define MC_ME_PRTN2_COFB0_STAT_BLOCK17_MASK (0x20000U) 1381 #define MC_ME_PRTN2_COFB0_STAT_BLOCK17_SHIFT (17U) 1382 #define MC_ME_PRTN2_COFB0_STAT_BLOCK17_WIDTH (1U) 1383 #define MC_ME_PRTN2_COFB0_STAT_BLOCK17(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK17_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK17_MASK) 1384 1385 #define MC_ME_PRTN2_COFB0_STAT_BLOCK18_MASK (0x40000U) 1386 #define MC_ME_PRTN2_COFB0_STAT_BLOCK18_SHIFT (18U) 1387 #define MC_ME_PRTN2_COFB0_STAT_BLOCK18_WIDTH (1U) 1388 #define MC_ME_PRTN2_COFB0_STAT_BLOCK18(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK18_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK18_MASK) 1389 1390 #define MC_ME_PRTN2_COFB0_STAT_BLOCK19_MASK (0x80000U) 1391 #define MC_ME_PRTN2_COFB0_STAT_BLOCK19_SHIFT (19U) 1392 #define MC_ME_PRTN2_COFB0_STAT_BLOCK19_WIDTH (1U) 1393 #define MC_ME_PRTN2_COFB0_STAT_BLOCK19(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK19_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK19_MASK) 1394 1395 #define MC_ME_PRTN2_COFB0_STAT_BLOCK20_MASK (0x100000U) 1396 #define MC_ME_PRTN2_COFB0_STAT_BLOCK20_SHIFT (20U) 1397 #define MC_ME_PRTN2_COFB0_STAT_BLOCK20_WIDTH (1U) 1398 #define MC_ME_PRTN2_COFB0_STAT_BLOCK20(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK20_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK20_MASK) 1399 1400 #define MC_ME_PRTN2_COFB0_STAT_BLOCK21_MASK (0x200000U) 1401 #define MC_ME_PRTN2_COFB0_STAT_BLOCK21_SHIFT (21U) 1402 #define MC_ME_PRTN2_COFB0_STAT_BLOCK21_WIDTH (1U) 1403 #define MC_ME_PRTN2_COFB0_STAT_BLOCK21(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK21_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK21_MASK) 1404 1405 #define MC_ME_PRTN2_COFB0_STAT_BLOCK22_MASK (0x400000U) 1406 #define MC_ME_PRTN2_COFB0_STAT_BLOCK22_SHIFT (22U) 1407 #define MC_ME_PRTN2_COFB0_STAT_BLOCK22_WIDTH (1U) 1408 #define MC_ME_PRTN2_COFB0_STAT_BLOCK22(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK22_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK22_MASK) 1409 1410 #define MC_ME_PRTN2_COFB0_STAT_BLOCK23_MASK (0x800000U) 1411 #define MC_ME_PRTN2_COFB0_STAT_BLOCK23_SHIFT (23U) 1412 #define MC_ME_PRTN2_COFB0_STAT_BLOCK23_WIDTH (1U) 1413 #define MC_ME_PRTN2_COFB0_STAT_BLOCK23(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK23_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK23_MASK) 1414 1415 #define MC_ME_PRTN2_COFB0_STAT_BLOCK24_MASK (0x1000000U) 1416 #define MC_ME_PRTN2_COFB0_STAT_BLOCK24_SHIFT (24U) 1417 #define MC_ME_PRTN2_COFB0_STAT_BLOCK24_WIDTH (1U) 1418 #define MC_ME_PRTN2_COFB0_STAT_BLOCK24(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK24_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK24_MASK) 1419 1420 #define MC_ME_PRTN2_COFB0_STAT_BLOCK25_MASK (0x2000000U) 1421 #define MC_ME_PRTN2_COFB0_STAT_BLOCK25_SHIFT (25U) 1422 #define MC_ME_PRTN2_COFB0_STAT_BLOCK25_WIDTH (1U) 1423 #define MC_ME_PRTN2_COFB0_STAT_BLOCK25(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK25_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK25_MASK) 1424 1425 #define MC_ME_PRTN2_COFB0_STAT_BLOCK29_MASK (0x20000000U) 1426 #define MC_ME_PRTN2_COFB0_STAT_BLOCK29_SHIFT (29U) 1427 #define MC_ME_PRTN2_COFB0_STAT_BLOCK29_WIDTH (1U) 1428 #define MC_ME_PRTN2_COFB0_STAT_BLOCK29(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_STAT_BLOCK29_SHIFT)) & MC_ME_PRTN2_COFB0_STAT_BLOCK29_MASK) 1429 /*! @} */ 1430 1431 /*! @name PRTN2_COFB1_STAT - Partition 2 COFB Set 1 Clock Status Register */ 1432 /*! @{ */ 1433 1434 #define MC_ME_PRTN2_COFB1_STAT_BLOCK32_MASK (0x1U) 1435 #define MC_ME_PRTN2_COFB1_STAT_BLOCK32_SHIFT (0U) 1436 #define MC_ME_PRTN2_COFB1_STAT_BLOCK32_WIDTH (1U) 1437 #define MC_ME_PRTN2_COFB1_STAT_BLOCK32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK32_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK32_MASK) 1438 1439 #define MC_ME_PRTN2_COFB1_STAT_BLOCK35_MASK (0x8U) 1440 #define MC_ME_PRTN2_COFB1_STAT_BLOCK35_SHIFT (3U) 1441 #define MC_ME_PRTN2_COFB1_STAT_BLOCK35_WIDTH (1U) 1442 #define MC_ME_PRTN2_COFB1_STAT_BLOCK35(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK35_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK35_MASK) 1443 1444 #define MC_ME_PRTN2_COFB1_STAT_BLOCK36_MASK (0x10U) 1445 #define MC_ME_PRTN2_COFB1_STAT_BLOCK36_SHIFT (4U) 1446 #define MC_ME_PRTN2_COFB1_STAT_BLOCK36_WIDTH (1U) 1447 #define MC_ME_PRTN2_COFB1_STAT_BLOCK36(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK36_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK36_MASK) 1448 1449 #define MC_ME_PRTN2_COFB1_STAT_BLOCK37_MASK (0x20U) 1450 #define MC_ME_PRTN2_COFB1_STAT_BLOCK37_SHIFT (5U) 1451 #define MC_ME_PRTN2_COFB1_STAT_BLOCK37_WIDTH (1U) 1452 #define MC_ME_PRTN2_COFB1_STAT_BLOCK37(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK37_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK37_MASK) 1453 1454 #define MC_ME_PRTN2_COFB1_STAT_BLOCK38_MASK (0x40U) 1455 #define MC_ME_PRTN2_COFB1_STAT_BLOCK38_SHIFT (6U) 1456 #define MC_ME_PRTN2_COFB1_STAT_BLOCK38_WIDTH (1U) 1457 #define MC_ME_PRTN2_COFB1_STAT_BLOCK38(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK38_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK38_MASK) 1458 1459 #define MC_ME_PRTN2_COFB1_STAT_BLOCK39_MASK (0x80U) 1460 #define MC_ME_PRTN2_COFB1_STAT_BLOCK39_SHIFT (7U) 1461 #define MC_ME_PRTN2_COFB1_STAT_BLOCK39_WIDTH (1U) 1462 #define MC_ME_PRTN2_COFB1_STAT_BLOCK39(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK39_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK39_MASK) 1463 1464 #define MC_ME_PRTN2_COFB1_STAT_BLOCK40_MASK (0x100U) 1465 #define MC_ME_PRTN2_COFB1_STAT_BLOCK40_SHIFT (8U) 1466 #define MC_ME_PRTN2_COFB1_STAT_BLOCK40_WIDTH (1U) 1467 #define MC_ME_PRTN2_COFB1_STAT_BLOCK40(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK40_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK40_MASK) 1468 1469 #define MC_ME_PRTN2_COFB1_STAT_BLOCK41_MASK (0x200U) 1470 #define MC_ME_PRTN2_COFB1_STAT_BLOCK41_SHIFT (9U) 1471 #define MC_ME_PRTN2_COFB1_STAT_BLOCK41_WIDTH (1U) 1472 #define MC_ME_PRTN2_COFB1_STAT_BLOCK41(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK41_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK41_MASK) 1473 1474 #define MC_ME_PRTN2_COFB1_STAT_BLOCK42_MASK (0x400U) 1475 #define MC_ME_PRTN2_COFB1_STAT_BLOCK42_SHIFT (10U) 1476 #define MC_ME_PRTN2_COFB1_STAT_BLOCK42_WIDTH (1U) 1477 #define MC_ME_PRTN2_COFB1_STAT_BLOCK42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK42_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK42_MASK) 1478 1479 #define MC_ME_PRTN2_COFB1_STAT_BLOCK47_MASK (0x8000U) 1480 #define MC_ME_PRTN2_COFB1_STAT_BLOCK47_SHIFT (15U) 1481 #define MC_ME_PRTN2_COFB1_STAT_BLOCK47_WIDTH (1U) 1482 #define MC_ME_PRTN2_COFB1_STAT_BLOCK47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK47_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK47_MASK) 1483 1484 #define MC_ME_PRTN2_COFB1_STAT_BLOCK48_MASK (0x10000U) 1485 #define MC_ME_PRTN2_COFB1_STAT_BLOCK48_SHIFT (16U) 1486 #define MC_ME_PRTN2_COFB1_STAT_BLOCK48_WIDTH (1U) 1487 #define MC_ME_PRTN2_COFB1_STAT_BLOCK48(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK48_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK48_MASK) 1488 1489 #define MC_ME_PRTN2_COFB1_STAT_BLOCK51_MASK (0x80000U) 1490 #define MC_ME_PRTN2_COFB1_STAT_BLOCK51_SHIFT (19U) 1491 #define MC_ME_PRTN2_COFB1_STAT_BLOCK51_WIDTH (1U) 1492 #define MC_ME_PRTN2_COFB1_STAT_BLOCK51(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK51_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK51_MASK) 1493 1494 #define MC_ME_PRTN2_COFB1_STAT_BLOCK55_MASK (0x800000U) 1495 #define MC_ME_PRTN2_COFB1_STAT_BLOCK55_SHIFT (23U) 1496 #define MC_ME_PRTN2_COFB1_STAT_BLOCK55_WIDTH (1U) 1497 #define MC_ME_PRTN2_COFB1_STAT_BLOCK55(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK55_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK55_MASK) 1498 1499 #define MC_ME_PRTN2_COFB1_STAT_BLOCK58_MASK (0x4000000U) 1500 #define MC_ME_PRTN2_COFB1_STAT_BLOCK58_SHIFT (26U) 1501 #define MC_ME_PRTN2_COFB1_STAT_BLOCK58_WIDTH (1U) 1502 #define MC_ME_PRTN2_COFB1_STAT_BLOCK58(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK58_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK58_MASK) 1503 1504 #define MC_ME_PRTN2_COFB1_STAT_BLOCK59_MASK (0x8000000U) 1505 #define MC_ME_PRTN2_COFB1_STAT_BLOCK59_SHIFT (27U) 1506 #define MC_ME_PRTN2_COFB1_STAT_BLOCK59_WIDTH (1U) 1507 #define MC_ME_PRTN2_COFB1_STAT_BLOCK59(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK59_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK59_MASK) 1508 1509 #define MC_ME_PRTN2_COFB1_STAT_BLOCK62_MASK (0x40000000U) 1510 #define MC_ME_PRTN2_COFB1_STAT_BLOCK62_SHIFT (30U) 1511 #define MC_ME_PRTN2_COFB1_STAT_BLOCK62_WIDTH (1U) 1512 #define MC_ME_PRTN2_COFB1_STAT_BLOCK62(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK62_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK62_MASK) 1513 1514 #define MC_ME_PRTN2_COFB1_STAT_BLOCK63_MASK (0x80000000U) 1515 #define MC_ME_PRTN2_COFB1_STAT_BLOCK63_SHIFT (31U) 1516 #define MC_ME_PRTN2_COFB1_STAT_BLOCK63_WIDTH (1U) 1517 #define MC_ME_PRTN2_COFB1_STAT_BLOCK63(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_STAT_BLOCK63_SHIFT)) & MC_ME_PRTN2_COFB1_STAT_BLOCK63_MASK) 1518 /*! @} */ 1519 1520 /*! @name PRTN2_COFB0_CLKEN - Partition 2 COFB Set 0 Clock Enable Register */ 1521 /*! @{ */ 1522 1523 #define MC_ME_PRTN2_COFB0_CLKEN_REQ4_MASK (0x10U) 1524 #define MC_ME_PRTN2_COFB0_CLKEN_REQ4_SHIFT (4U) 1525 #define MC_ME_PRTN2_COFB0_CLKEN_REQ4_WIDTH (1U) 1526 #define MC_ME_PRTN2_COFB0_CLKEN_REQ4(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ4_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ4_MASK) 1527 1528 #define MC_ME_PRTN2_COFB0_CLKEN_REQ5_MASK (0x20U) 1529 #define MC_ME_PRTN2_COFB0_CLKEN_REQ5_SHIFT (5U) 1530 #define MC_ME_PRTN2_COFB0_CLKEN_REQ5_WIDTH (1U) 1531 #define MC_ME_PRTN2_COFB0_CLKEN_REQ5(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ5_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ5_MASK) 1532 1533 #define MC_ME_PRTN2_COFB0_CLKEN_REQ6_MASK (0x40U) 1534 #define MC_ME_PRTN2_COFB0_CLKEN_REQ6_SHIFT (6U) 1535 #define MC_ME_PRTN2_COFB0_CLKEN_REQ6_WIDTH (1U) 1536 #define MC_ME_PRTN2_COFB0_CLKEN_REQ6(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ6_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ6_MASK) 1537 1538 #define MC_ME_PRTN2_COFB0_CLKEN_REQ7_MASK (0x80U) 1539 #define MC_ME_PRTN2_COFB0_CLKEN_REQ7_SHIFT (7U) 1540 #define MC_ME_PRTN2_COFB0_CLKEN_REQ7_WIDTH (1U) 1541 #define MC_ME_PRTN2_COFB0_CLKEN_REQ7(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ7_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ7_MASK) 1542 1543 #define MC_ME_PRTN2_COFB0_CLKEN_REQ8_MASK (0x100U) 1544 #define MC_ME_PRTN2_COFB0_CLKEN_REQ8_SHIFT (8U) 1545 #define MC_ME_PRTN2_COFB0_CLKEN_REQ8_WIDTH (1U) 1546 #define MC_ME_PRTN2_COFB0_CLKEN_REQ8(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ8_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ8_MASK) 1547 1548 #define MC_ME_PRTN2_COFB0_CLKEN_REQ9_MASK (0x200U) 1549 #define MC_ME_PRTN2_COFB0_CLKEN_REQ9_SHIFT (9U) 1550 #define MC_ME_PRTN2_COFB0_CLKEN_REQ9_WIDTH (1U) 1551 #define MC_ME_PRTN2_COFB0_CLKEN_REQ9(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ9_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ9_MASK) 1552 1553 #define MC_ME_PRTN2_COFB0_CLKEN_REQ10_MASK (0x400U) 1554 #define MC_ME_PRTN2_COFB0_CLKEN_REQ10_SHIFT (10U) 1555 #define MC_ME_PRTN2_COFB0_CLKEN_REQ10_WIDTH (1U) 1556 #define MC_ME_PRTN2_COFB0_CLKEN_REQ10(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ10_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ10_MASK) 1557 1558 #define MC_ME_PRTN2_COFB0_CLKEN_REQ11_MASK (0x800U) 1559 #define MC_ME_PRTN2_COFB0_CLKEN_REQ11_SHIFT (11U) 1560 #define MC_ME_PRTN2_COFB0_CLKEN_REQ11_WIDTH (1U) 1561 #define MC_ME_PRTN2_COFB0_CLKEN_REQ11(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ11_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ11_MASK) 1562 1563 #define MC_ME_PRTN2_COFB0_CLKEN_REQ12_MASK (0x1000U) 1564 #define MC_ME_PRTN2_COFB0_CLKEN_REQ12_SHIFT (12U) 1565 #define MC_ME_PRTN2_COFB0_CLKEN_REQ12_WIDTH (1U) 1566 #define MC_ME_PRTN2_COFB0_CLKEN_REQ12(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ12_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ12_MASK) 1567 1568 #define MC_ME_PRTN2_COFB0_CLKEN_REQ13_MASK (0x2000U) 1569 #define MC_ME_PRTN2_COFB0_CLKEN_REQ13_SHIFT (13U) 1570 #define MC_ME_PRTN2_COFB0_CLKEN_REQ13_WIDTH (1U) 1571 #define MC_ME_PRTN2_COFB0_CLKEN_REQ13(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ13_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ13_MASK) 1572 1573 #define MC_ME_PRTN2_COFB0_CLKEN_REQ14_MASK (0x4000U) 1574 #define MC_ME_PRTN2_COFB0_CLKEN_REQ14_SHIFT (14U) 1575 #define MC_ME_PRTN2_COFB0_CLKEN_REQ14_WIDTH (1U) 1576 #define MC_ME_PRTN2_COFB0_CLKEN_REQ14(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ14_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ14_MASK) 1577 1578 #define MC_ME_PRTN2_COFB0_CLKEN_REQ15_MASK (0x8000U) 1579 #define MC_ME_PRTN2_COFB0_CLKEN_REQ15_SHIFT (15U) 1580 #define MC_ME_PRTN2_COFB0_CLKEN_REQ15_WIDTH (1U) 1581 #define MC_ME_PRTN2_COFB0_CLKEN_REQ15(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ15_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ15_MASK) 1582 1583 #define MC_ME_PRTN2_COFB0_CLKEN_REQ16_MASK (0x10000U) 1584 #define MC_ME_PRTN2_COFB0_CLKEN_REQ16_SHIFT (16U) 1585 #define MC_ME_PRTN2_COFB0_CLKEN_REQ16_WIDTH (1U) 1586 #define MC_ME_PRTN2_COFB0_CLKEN_REQ16(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ16_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ16_MASK) 1587 1588 #define MC_ME_PRTN2_COFB0_CLKEN_REQ17_MASK (0x20000U) 1589 #define MC_ME_PRTN2_COFB0_CLKEN_REQ17_SHIFT (17U) 1590 #define MC_ME_PRTN2_COFB0_CLKEN_REQ17_WIDTH (1U) 1591 #define MC_ME_PRTN2_COFB0_CLKEN_REQ17(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ17_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ17_MASK) 1592 1593 #define MC_ME_PRTN2_COFB0_CLKEN_REQ18_MASK (0x40000U) 1594 #define MC_ME_PRTN2_COFB0_CLKEN_REQ18_SHIFT (18U) 1595 #define MC_ME_PRTN2_COFB0_CLKEN_REQ18_WIDTH (1U) 1596 #define MC_ME_PRTN2_COFB0_CLKEN_REQ18(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ18_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ18_MASK) 1597 1598 #define MC_ME_PRTN2_COFB0_CLKEN_REQ19_MASK (0x80000U) 1599 #define MC_ME_PRTN2_COFB0_CLKEN_REQ19_SHIFT (19U) 1600 #define MC_ME_PRTN2_COFB0_CLKEN_REQ19_WIDTH (1U) 1601 #define MC_ME_PRTN2_COFB0_CLKEN_REQ19(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ19_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ19_MASK) 1602 1603 #define MC_ME_PRTN2_COFB0_CLKEN_REQ20_MASK (0x100000U) 1604 #define MC_ME_PRTN2_COFB0_CLKEN_REQ20_SHIFT (20U) 1605 #define MC_ME_PRTN2_COFB0_CLKEN_REQ20_WIDTH (1U) 1606 #define MC_ME_PRTN2_COFB0_CLKEN_REQ20(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ20_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ20_MASK) 1607 1608 #define MC_ME_PRTN2_COFB0_CLKEN_REQ21_MASK (0x200000U) 1609 #define MC_ME_PRTN2_COFB0_CLKEN_REQ21_SHIFT (21U) 1610 #define MC_ME_PRTN2_COFB0_CLKEN_REQ21_WIDTH (1U) 1611 #define MC_ME_PRTN2_COFB0_CLKEN_REQ21(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ21_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ21_MASK) 1612 1613 #define MC_ME_PRTN2_COFB0_CLKEN_REQ22_MASK (0x400000U) 1614 #define MC_ME_PRTN2_COFB0_CLKEN_REQ22_SHIFT (22U) 1615 #define MC_ME_PRTN2_COFB0_CLKEN_REQ22_WIDTH (1U) 1616 #define MC_ME_PRTN2_COFB0_CLKEN_REQ22(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ22_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ22_MASK) 1617 1618 #define MC_ME_PRTN2_COFB0_CLKEN_REQ23_MASK (0x800000U) 1619 #define MC_ME_PRTN2_COFB0_CLKEN_REQ23_SHIFT (23U) 1620 #define MC_ME_PRTN2_COFB0_CLKEN_REQ23_WIDTH (1U) 1621 #define MC_ME_PRTN2_COFB0_CLKEN_REQ23(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ23_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ23_MASK) 1622 1623 #define MC_ME_PRTN2_COFB0_CLKEN_REQ24_MASK (0x1000000U) 1624 #define MC_ME_PRTN2_COFB0_CLKEN_REQ24_SHIFT (24U) 1625 #define MC_ME_PRTN2_COFB0_CLKEN_REQ24_WIDTH (1U) 1626 #define MC_ME_PRTN2_COFB0_CLKEN_REQ24(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ24_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ24_MASK) 1627 1628 #define MC_ME_PRTN2_COFB0_CLKEN_REQ29_MASK (0x20000000U) 1629 #define MC_ME_PRTN2_COFB0_CLKEN_REQ29_SHIFT (29U) 1630 #define MC_ME_PRTN2_COFB0_CLKEN_REQ29_WIDTH (1U) 1631 #define MC_ME_PRTN2_COFB0_CLKEN_REQ29(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB0_CLKEN_REQ29_SHIFT)) & MC_ME_PRTN2_COFB0_CLKEN_REQ29_MASK) 1632 /*! @} */ 1633 1634 /*! @name PRTN2_COFB1_CLKEN - Partition 2 COFB Set 1 Clock Enable Register */ 1635 /*! @{ */ 1636 1637 #define MC_ME_PRTN2_COFB1_CLKEN_REQ32_MASK (0x1U) 1638 #define MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT (0U) 1639 #define MC_ME_PRTN2_COFB1_CLKEN_REQ32_WIDTH (1U) 1640 #define MC_ME_PRTN2_COFB1_CLKEN_REQ32(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ32_MASK) 1641 1642 #define MC_ME_PRTN2_COFB1_CLKEN_REQ35_MASK (0x8U) 1643 #define MC_ME_PRTN2_COFB1_CLKEN_REQ35_SHIFT (3U) 1644 #define MC_ME_PRTN2_COFB1_CLKEN_REQ35_WIDTH (1U) 1645 #define MC_ME_PRTN2_COFB1_CLKEN_REQ35(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ35_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ35_MASK) 1646 1647 #define MC_ME_PRTN2_COFB1_CLKEN_REQ36_MASK (0x10U) 1648 #define MC_ME_PRTN2_COFB1_CLKEN_REQ36_SHIFT (4U) 1649 #define MC_ME_PRTN2_COFB1_CLKEN_REQ36_WIDTH (1U) 1650 #define MC_ME_PRTN2_COFB1_CLKEN_REQ36(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ36_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ36_MASK) 1651 1652 #define MC_ME_PRTN2_COFB1_CLKEN_REQ37_MASK (0x20U) 1653 #define MC_ME_PRTN2_COFB1_CLKEN_REQ37_SHIFT (5U) 1654 #define MC_ME_PRTN2_COFB1_CLKEN_REQ37_WIDTH (1U) 1655 #define MC_ME_PRTN2_COFB1_CLKEN_REQ37(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ37_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ37_MASK) 1656 1657 #define MC_ME_PRTN2_COFB1_CLKEN_REQ38_MASK (0x40U) 1658 #define MC_ME_PRTN2_COFB1_CLKEN_REQ38_SHIFT (6U) 1659 #define MC_ME_PRTN2_COFB1_CLKEN_REQ38_WIDTH (1U) 1660 #define MC_ME_PRTN2_COFB1_CLKEN_REQ38(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ38_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ38_MASK) 1661 1662 #define MC_ME_PRTN2_COFB1_CLKEN_REQ39_MASK (0x80U) 1663 #define MC_ME_PRTN2_COFB1_CLKEN_REQ39_SHIFT (7U) 1664 #define MC_ME_PRTN2_COFB1_CLKEN_REQ39_WIDTH (1U) 1665 #define MC_ME_PRTN2_COFB1_CLKEN_REQ39(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ39_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ39_MASK) 1666 1667 #define MC_ME_PRTN2_COFB1_CLKEN_REQ40_MASK (0x100U) 1668 #define MC_ME_PRTN2_COFB1_CLKEN_REQ40_SHIFT (8U) 1669 #define MC_ME_PRTN2_COFB1_CLKEN_REQ40_WIDTH (1U) 1670 #define MC_ME_PRTN2_COFB1_CLKEN_REQ40(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ40_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ40_MASK) 1671 1672 #define MC_ME_PRTN2_COFB1_CLKEN_REQ41_MASK (0x200U) 1673 #define MC_ME_PRTN2_COFB1_CLKEN_REQ41_SHIFT (9U) 1674 #define MC_ME_PRTN2_COFB1_CLKEN_REQ41_WIDTH (1U) 1675 #define MC_ME_PRTN2_COFB1_CLKEN_REQ41(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ41_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ41_MASK) 1676 1677 #define MC_ME_PRTN2_COFB1_CLKEN_REQ42_MASK (0x400U) 1678 #define MC_ME_PRTN2_COFB1_CLKEN_REQ42_SHIFT (10U) 1679 #define MC_ME_PRTN2_COFB1_CLKEN_REQ42_WIDTH (1U) 1680 #define MC_ME_PRTN2_COFB1_CLKEN_REQ42(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ42_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ42_MASK) 1681 1682 #define MC_ME_PRTN2_COFB1_CLKEN_REQ47_MASK (0x8000U) 1683 #define MC_ME_PRTN2_COFB1_CLKEN_REQ47_SHIFT (15U) 1684 #define MC_ME_PRTN2_COFB1_CLKEN_REQ47_WIDTH (1U) 1685 #define MC_ME_PRTN2_COFB1_CLKEN_REQ47(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ47_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ47_MASK) 1686 1687 #define MC_ME_PRTN2_COFB1_CLKEN_REQ48_MASK (0x10000U) 1688 #define MC_ME_PRTN2_COFB1_CLKEN_REQ48_SHIFT (16U) 1689 #define MC_ME_PRTN2_COFB1_CLKEN_REQ48_WIDTH (1U) 1690 #define MC_ME_PRTN2_COFB1_CLKEN_REQ48(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ48_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ48_MASK) 1691 1692 #define MC_ME_PRTN2_COFB1_CLKEN_REQ51_MASK (0x80000U) 1693 #define MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT (19U) 1694 #define MC_ME_PRTN2_COFB1_CLKEN_REQ51_WIDTH (1U) 1695 #define MC_ME_PRTN2_COFB1_CLKEN_REQ51(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ51_MASK) 1696 1697 #define MC_ME_PRTN2_COFB1_CLKEN_REQ55_MASK (0x800000U) 1698 #define MC_ME_PRTN2_COFB1_CLKEN_REQ55_SHIFT (23U) 1699 #define MC_ME_PRTN2_COFB1_CLKEN_REQ55_WIDTH (1U) 1700 #define MC_ME_PRTN2_COFB1_CLKEN_REQ55(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ55_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ55_MASK) 1701 1702 #define MC_ME_PRTN2_COFB1_CLKEN_REQ58_MASK (0x4000000U) 1703 #define MC_ME_PRTN2_COFB1_CLKEN_REQ58_SHIFT (26U) 1704 #define MC_ME_PRTN2_COFB1_CLKEN_REQ58_WIDTH (1U) 1705 #define MC_ME_PRTN2_COFB1_CLKEN_REQ58(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ58_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ58_MASK) 1706 1707 #define MC_ME_PRTN2_COFB1_CLKEN_REQ62_MASK (0x40000000U) 1708 #define MC_ME_PRTN2_COFB1_CLKEN_REQ62_SHIFT (30U) 1709 #define MC_ME_PRTN2_COFB1_CLKEN_REQ62_WIDTH (1U) 1710 #define MC_ME_PRTN2_COFB1_CLKEN_REQ62(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ62_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ62_MASK) 1711 1712 #define MC_ME_PRTN2_COFB1_CLKEN_REQ63_MASK (0x80000000U) 1713 #define MC_ME_PRTN2_COFB1_CLKEN_REQ63_SHIFT (31U) 1714 #define MC_ME_PRTN2_COFB1_CLKEN_REQ63_WIDTH (1U) 1715 #define MC_ME_PRTN2_COFB1_CLKEN_REQ63(x) (((uint32_t)(((uint32_t)(x)) << MC_ME_PRTN2_COFB1_CLKEN_REQ63_SHIFT)) & MC_ME_PRTN2_COFB1_CLKEN_REQ63_MASK) 1716 /*! @} */ 1717 1718 /*! 1719 * @} 1720 */ /* end of group MC_ME_Register_Masks */ 1721 1722 /*! 1723 * @} 1724 */ /* end of group MC_ME_Peripheral_Access_Layer */ 1725 1726 #endif /* #if !defined(S32K344_MC_ME_H_) */ 1727
