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Searched refs:LPTMR1_IRQn (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h110 LPTMR1_IRQn = 32, /**< LPTMR1 interrupt (INTMUX source IRQ0) */ enumerator
9607 LPTMR0_IRQn, LPTMR1_IRQn \
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h110 LPTMR1_IRQn = 32, /**< LPTMR1 interrupt (INTMUX source IRQ0) */ enumerator
9607 LPTMR0_IRQn, LPTMR1_IRQn \
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h114 LPTMR1_IRQn = 39, /**< LPTMR1 interrupt (INTMUX1 source IRQ7) */ enumerator
11228 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn }
DK32L3A60_cm4.h109 LPTMR1_IRQn = 30, /**< LPTMR1 interrupt */ enumerator
11863 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h129 LPTMR1_IRQn = 37, /**< Low Power Timer */ enumerator
14186 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h130 LPTMR1_IRQn = 37, /**< Low Power Timer */ enumerator
14187 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
51075 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
DMCXN946_cm33_core1.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
51075 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core1.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
50602 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
DMCXN547_cm33_core0.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
50602 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
50602 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
DMCXN546_cm33_core1.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
50602 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core0.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
51075 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
DMCXN947_cm33_core1.h226 LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ enumerator
51075 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h99 LPTMR1_IRQn = 18, /**< Low Power Timer 1 */ enumerator
49452 NotAvail_IRQn, LPTMR1_IRQn, LPTMR2_IRQn \
DMIMX9352_ca55.h114 LPTMR1_IRQn = 50, /**< Low Power Timer 1 */ enumerator
44174 #define LPTMR_IRQS { NotAvail_IRQn, LPTMR1_IRQn, LPTMR2_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h179 LPTMR1_IRQn = 91, /**< Low Power Timer 1 */ enumerator
33740 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h179 LPTMR1_IRQn = 91, /**< Low Power Timer 1 */ enumerator
33740 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h179 LPTMR1_IRQn = 91, /**< Low Power Timer 1 */ enumerator
32132 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US3/
DMIMX8US3_cm33.h179 LPTMR1_IRQn = 91, /**< Low Power Timer 1 */ enumerator
33740 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US5/
DMIMX8US5_cm33.h179 LPTMR1_IRQn = 91, /**< Low Power Timer 1 */ enumerator
32132 #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn }