1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_LPSPI.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_LPSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_LPSPI_H_) /* Check if memory map has not been already included */ 58 #define S32K344_LPSPI_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPSPI - Size of Registers Arrays */ 72 #define LPSPI_TDBR_COUNT 128u 73 #define LPSPI_RDBR_COUNT 128u 74 75 /** LPSPI - Register Layout Typedef */ 76 typedef struct { 77 __I uint32_t VERID; /**< Version ID, offset: 0x0 */ 78 __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ 79 uint8_t RESERVED_0[8]; 80 __IO uint32_t CR; /**< Control, offset: 0x10 */ 81 __IO uint32_t SR; /**< Status, offset: 0x14 */ 82 __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ 83 __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ 84 __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ 85 __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ 86 uint8_t RESERVED_1[8]; 87 __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ 88 __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ 89 uint8_t RESERVED_2[8]; 90 __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ 91 __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ 92 uint8_t RESERVED_3[16]; 93 __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ 94 __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ 95 __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ 96 __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ 97 uint8_t RESERVED_4[8]; 98 __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ 99 __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ 100 __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ 101 uint8_t RESERVED_5[896]; 102 __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ 103 __O uint32_t TDBR[LPSPI_TDBR_COUNT]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ 104 __I uint32_t RDBR[LPSPI_RDBR_COUNT]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ 105 } LPSPI_Type, *LPSPI_MemMapPtr; 106 107 /** Number of instances of the LPSPI module. */ 108 #define LPSPI_INSTANCE_COUNT (6u) 109 110 /* LPSPI - Peripheral instance base addresses */ 111 /** Peripheral LPSPI_0 base address */ 112 #define IP_LPSPI_0_BASE (0x40358000u) 113 /** Peripheral LPSPI_0 base pointer */ 114 #define IP_LPSPI_0 ((LPSPI_Type *)IP_LPSPI_0_BASE) 115 /** Peripheral LPSPI_1 base address */ 116 #define IP_LPSPI_1_BASE (0x4035C000u) 117 /** Peripheral LPSPI_1 base pointer */ 118 #define IP_LPSPI_1 ((LPSPI_Type *)IP_LPSPI_1_BASE) 119 /** Peripheral LPSPI_2 base address */ 120 #define IP_LPSPI_2_BASE (0x40360000u) 121 /** Peripheral LPSPI_2 base pointer */ 122 #define IP_LPSPI_2 ((LPSPI_Type *)IP_LPSPI_2_BASE) 123 /** Peripheral LPSPI_3 base address */ 124 #define IP_LPSPI_3_BASE (0x40364000u) 125 /** Peripheral LPSPI_3 base pointer */ 126 #define IP_LPSPI_3 ((LPSPI_Type *)IP_LPSPI_3_BASE) 127 /** Peripheral LPSPI_4 base address */ 128 #define IP_LPSPI_4_BASE (0x404BC000u) 129 /** Peripheral LPSPI_4 base pointer */ 130 #define IP_LPSPI_4 ((LPSPI_Type *)IP_LPSPI_4_BASE) 131 /** Peripheral LPSPI_5 base address */ 132 #define IP_LPSPI_5_BASE (0x404C0000u) 133 /** Peripheral LPSPI_5 base pointer */ 134 #define IP_LPSPI_5 ((LPSPI_Type *)IP_LPSPI_5_BASE) 135 /** Array initializer of LPSPI peripheral base addresses */ 136 #define IP_LPSPI_BASE_ADDRS { IP_LPSPI_0_BASE, IP_LPSPI_1_BASE, IP_LPSPI_2_BASE, IP_LPSPI_3_BASE, IP_LPSPI_4_BASE, IP_LPSPI_5_BASE } 137 /** Array initializer of LPSPI peripheral base pointers */ 138 #define IP_LPSPI_BASE_PTRS { IP_LPSPI_0, IP_LPSPI_1, IP_LPSPI_2, IP_LPSPI_3, IP_LPSPI_4, IP_LPSPI_5 } 139 140 /* ---------------------------------------------------------------------------- 141 -- LPSPI Register Masks 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks 146 * @{ 147 */ 148 149 /*! @name VERID - Version ID */ 150 /*! @{ */ 151 152 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) 153 #define LPSPI_VERID_FEATURE_SHIFT (0U) 154 #define LPSPI_VERID_FEATURE_WIDTH (16U) 155 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) 156 157 #define LPSPI_VERID_MINOR_MASK (0xFF0000U) 158 #define LPSPI_VERID_MINOR_SHIFT (16U) 159 #define LPSPI_VERID_MINOR_WIDTH (8U) 160 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) 161 162 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) 163 #define LPSPI_VERID_MAJOR_SHIFT (24U) 164 #define LPSPI_VERID_MAJOR_WIDTH (8U) 165 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) 166 /*! @} */ 167 168 /*! @name PARAM - Parameter */ 169 /*! @{ */ 170 171 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) 172 #define LPSPI_PARAM_TXFIFO_SHIFT (0U) 173 #define LPSPI_PARAM_TXFIFO_WIDTH (8U) 174 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) 175 176 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) 177 #define LPSPI_PARAM_RXFIFO_SHIFT (8U) 178 #define LPSPI_PARAM_RXFIFO_WIDTH (8U) 179 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) 180 181 #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) 182 #define LPSPI_PARAM_PCSNUM_SHIFT (16U) 183 #define LPSPI_PARAM_PCSNUM_WIDTH (8U) 184 #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) 185 /*! @} */ 186 187 /*! @name CR - Control */ 188 /*! @{ */ 189 190 #define LPSPI_CR_MEN_MASK (0x1U) 191 #define LPSPI_CR_MEN_SHIFT (0U) 192 #define LPSPI_CR_MEN_WIDTH (1U) 193 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) 194 195 #define LPSPI_CR_RST_MASK (0x2U) 196 #define LPSPI_CR_RST_SHIFT (1U) 197 #define LPSPI_CR_RST_WIDTH (1U) 198 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) 199 200 #define LPSPI_CR_DBGEN_MASK (0x8U) 201 #define LPSPI_CR_DBGEN_SHIFT (3U) 202 #define LPSPI_CR_DBGEN_WIDTH (1U) 203 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) 204 205 #define LPSPI_CR_RTF_MASK (0x100U) 206 #define LPSPI_CR_RTF_SHIFT (8U) 207 #define LPSPI_CR_RTF_WIDTH (1U) 208 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) 209 210 #define LPSPI_CR_RRF_MASK (0x200U) 211 #define LPSPI_CR_RRF_SHIFT (9U) 212 #define LPSPI_CR_RRF_WIDTH (1U) 213 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) 214 /*! @} */ 215 216 /*! @name SR - Status */ 217 /*! @{ */ 218 219 #define LPSPI_SR_TDF_MASK (0x1U) 220 #define LPSPI_SR_TDF_SHIFT (0U) 221 #define LPSPI_SR_TDF_WIDTH (1U) 222 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) 223 224 #define LPSPI_SR_RDF_MASK (0x2U) 225 #define LPSPI_SR_RDF_SHIFT (1U) 226 #define LPSPI_SR_RDF_WIDTH (1U) 227 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) 228 229 #define LPSPI_SR_WCF_MASK (0x100U) 230 #define LPSPI_SR_WCF_SHIFT (8U) 231 #define LPSPI_SR_WCF_WIDTH (1U) 232 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) 233 234 #define LPSPI_SR_FCF_MASK (0x200U) 235 #define LPSPI_SR_FCF_SHIFT (9U) 236 #define LPSPI_SR_FCF_WIDTH (1U) 237 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) 238 239 #define LPSPI_SR_TCF_MASK (0x400U) 240 #define LPSPI_SR_TCF_SHIFT (10U) 241 #define LPSPI_SR_TCF_WIDTH (1U) 242 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) 243 244 #define LPSPI_SR_TEF_MASK (0x800U) 245 #define LPSPI_SR_TEF_SHIFT (11U) 246 #define LPSPI_SR_TEF_WIDTH (1U) 247 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) 248 249 #define LPSPI_SR_REF_MASK (0x1000U) 250 #define LPSPI_SR_REF_SHIFT (12U) 251 #define LPSPI_SR_REF_WIDTH (1U) 252 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) 253 254 #define LPSPI_SR_DMF_MASK (0x2000U) 255 #define LPSPI_SR_DMF_SHIFT (13U) 256 #define LPSPI_SR_DMF_WIDTH (1U) 257 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) 258 259 #define LPSPI_SR_MBF_MASK (0x1000000U) 260 #define LPSPI_SR_MBF_SHIFT (24U) 261 #define LPSPI_SR_MBF_WIDTH (1U) 262 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) 263 /*! @} */ 264 265 /*! @name IER - Interrupt Enable */ 266 /*! @{ */ 267 268 #define LPSPI_IER_TDIE_MASK (0x1U) 269 #define LPSPI_IER_TDIE_SHIFT (0U) 270 #define LPSPI_IER_TDIE_WIDTH (1U) 271 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) 272 273 #define LPSPI_IER_RDIE_MASK (0x2U) 274 #define LPSPI_IER_RDIE_SHIFT (1U) 275 #define LPSPI_IER_RDIE_WIDTH (1U) 276 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) 277 278 #define LPSPI_IER_WCIE_MASK (0x100U) 279 #define LPSPI_IER_WCIE_SHIFT (8U) 280 #define LPSPI_IER_WCIE_WIDTH (1U) 281 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) 282 283 #define LPSPI_IER_FCIE_MASK (0x200U) 284 #define LPSPI_IER_FCIE_SHIFT (9U) 285 #define LPSPI_IER_FCIE_WIDTH (1U) 286 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) 287 288 #define LPSPI_IER_TCIE_MASK (0x400U) 289 #define LPSPI_IER_TCIE_SHIFT (10U) 290 #define LPSPI_IER_TCIE_WIDTH (1U) 291 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) 292 293 #define LPSPI_IER_TEIE_MASK (0x800U) 294 #define LPSPI_IER_TEIE_SHIFT (11U) 295 #define LPSPI_IER_TEIE_WIDTH (1U) 296 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) 297 298 #define LPSPI_IER_REIE_MASK (0x1000U) 299 #define LPSPI_IER_REIE_SHIFT (12U) 300 #define LPSPI_IER_REIE_WIDTH (1U) 301 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) 302 303 #define LPSPI_IER_DMIE_MASK (0x2000U) 304 #define LPSPI_IER_DMIE_SHIFT (13U) 305 #define LPSPI_IER_DMIE_WIDTH (1U) 306 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) 307 /*! @} */ 308 309 /*! @name DER - DMA Enable */ 310 /*! @{ */ 311 312 #define LPSPI_DER_TDDE_MASK (0x1U) 313 #define LPSPI_DER_TDDE_SHIFT (0U) 314 #define LPSPI_DER_TDDE_WIDTH (1U) 315 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) 316 317 #define LPSPI_DER_RDDE_MASK (0x2U) 318 #define LPSPI_DER_RDDE_SHIFT (1U) 319 #define LPSPI_DER_RDDE_WIDTH (1U) 320 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) 321 /*! @} */ 322 323 /*! @name CFGR0 - Configuration 0 */ 324 /*! @{ */ 325 326 #define LPSPI_CFGR0_HREN_MASK (0x1U) 327 #define LPSPI_CFGR0_HREN_SHIFT (0U) 328 #define LPSPI_CFGR0_HREN_WIDTH (1U) 329 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) 330 331 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) 332 #define LPSPI_CFGR0_HRPOL_SHIFT (1U) 333 #define LPSPI_CFGR0_HRPOL_WIDTH (1U) 334 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) 335 336 #define LPSPI_CFGR0_HRSEL_MASK (0x4U) 337 #define LPSPI_CFGR0_HRSEL_SHIFT (2U) 338 #define LPSPI_CFGR0_HRSEL_WIDTH (1U) 339 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) 340 341 #define LPSPI_CFGR0_HRDIR_MASK (0x8U) 342 #define LPSPI_CFGR0_HRDIR_SHIFT (3U) 343 #define LPSPI_CFGR0_HRDIR_WIDTH (1U) 344 #define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) 345 346 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) 347 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) 348 #define LPSPI_CFGR0_CIRFIFO_WIDTH (1U) 349 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) 350 351 #define LPSPI_CFGR0_RDMO_MASK (0x200U) 352 #define LPSPI_CFGR0_RDMO_SHIFT (9U) 353 #define LPSPI_CFGR0_RDMO_WIDTH (1U) 354 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) 355 /*! @} */ 356 357 /*! @name CFGR1 - Configuration 1 */ 358 /*! @{ */ 359 360 #define LPSPI_CFGR1_MASTER_MASK (0x1U) 361 #define LPSPI_CFGR1_MASTER_SHIFT (0U) 362 #define LPSPI_CFGR1_MASTER_WIDTH (1U) 363 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) 364 365 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) 366 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) 367 #define LPSPI_CFGR1_SAMPLE_WIDTH (1U) 368 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) 369 370 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) 371 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) 372 #define LPSPI_CFGR1_AUTOPCS_WIDTH (1U) 373 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) 374 375 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) 376 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) 377 #define LPSPI_CFGR1_NOSTALL_WIDTH (1U) 378 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) 379 380 #define LPSPI_CFGR1_PARTIAL_MASK (0x10U) 381 #define LPSPI_CFGR1_PARTIAL_SHIFT (4U) 382 #define LPSPI_CFGR1_PARTIAL_WIDTH (1U) 383 #define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) 384 385 #define LPSPI_CFGR1_PCSPOL_MASK (0xFF00U) /* Merged from fields with different position or width, of widths (4, 6, 8), largest definition used */ 386 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) 387 #define LPSPI_CFGR1_PCSPOL_WIDTH (8U) 388 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) /* Merged from fields with different position or width, of widths (4, 6, 8), largest definition used */ 389 390 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) 391 #define LPSPI_CFGR1_MATCFG_SHIFT (16U) 392 #define LPSPI_CFGR1_MATCFG_WIDTH (3U) 393 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) 394 395 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) 396 #define LPSPI_CFGR1_PINCFG_SHIFT (24U) 397 #define LPSPI_CFGR1_PINCFG_WIDTH (2U) 398 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) 399 400 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) 401 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) 402 #define LPSPI_CFGR1_OUTCFG_WIDTH (1U) 403 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) 404 405 #define LPSPI_CFGR1_PCSCFG_MASK (0x18000000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ 406 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) 407 #define LPSPI_CFGR1_PCSCFG_WIDTH (2U) 408 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ 409 /*! @} */ 410 411 /*! @name DMR0 - Data Match 0 */ 412 /*! @{ */ 413 414 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) 415 #define LPSPI_DMR0_MATCH0_SHIFT (0U) 416 #define LPSPI_DMR0_MATCH0_WIDTH (32U) 417 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) 418 /*! @} */ 419 420 /*! @name DMR1 - Data Match 1 */ 421 /*! @{ */ 422 423 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) 424 #define LPSPI_DMR1_MATCH1_SHIFT (0U) 425 #define LPSPI_DMR1_MATCH1_WIDTH (32U) 426 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) 427 /*! @} */ 428 429 /*! @name CCR - Clock Configuration */ 430 /*! @{ */ 431 432 #define LPSPI_CCR_SCKDIV_MASK (0xFFU) 433 #define LPSPI_CCR_SCKDIV_SHIFT (0U) 434 #define LPSPI_CCR_SCKDIV_WIDTH (8U) 435 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) 436 437 #define LPSPI_CCR_DBT_MASK (0xFF00U) 438 #define LPSPI_CCR_DBT_SHIFT (8U) 439 #define LPSPI_CCR_DBT_WIDTH (8U) 440 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) 441 442 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) 443 #define LPSPI_CCR_PCSSCK_SHIFT (16U) 444 #define LPSPI_CCR_PCSSCK_WIDTH (8U) 445 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) 446 447 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) 448 #define LPSPI_CCR_SCKPCS_SHIFT (24U) 449 #define LPSPI_CCR_SCKPCS_WIDTH (8U) 450 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) 451 /*! @} */ 452 453 /*! @name CCR1 - Clock Configuration 1 */ 454 /*! @{ */ 455 456 #define LPSPI_CCR1_SCKSET_MASK (0xFFU) 457 #define LPSPI_CCR1_SCKSET_SHIFT (0U) 458 #define LPSPI_CCR1_SCKSET_WIDTH (8U) 459 #define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) 460 461 #define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) 462 #define LPSPI_CCR1_SCKHLD_SHIFT (8U) 463 #define LPSPI_CCR1_SCKHLD_WIDTH (8U) 464 #define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) 465 466 #define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) 467 #define LPSPI_CCR1_PCSPCS_SHIFT (16U) 468 #define LPSPI_CCR1_PCSPCS_WIDTH (8U) 469 #define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) 470 471 #define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) 472 #define LPSPI_CCR1_SCKSCK_SHIFT (24U) 473 #define LPSPI_CCR1_SCKSCK_WIDTH (8U) 474 #define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) 475 /*! @} */ 476 477 /*! @name FCR - FIFO Control */ 478 /*! @{ */ 479 480 #define LPSPI_FCR_TXWATER_MASK (0x3U) 481 #define LPSPI_FCR_TXWATER_SHIFT (0U) 482 #define LPSPI_FCR_TXWATER_WIDTH (2U) 483 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) 484 485 #define LPSPI_FCR_RXWATER_MASK (0x30000U) 486 #define LPSPI_FCR_RXWATER_SHIFT (16U) 487 #define LPSPI_FCR_RXWATER_WIDTH (2U) 488 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) 489 /*! @} */ 490 491 /*! @name FSR - FIFO Status */ 492 /*! @{ */ 493 494 #define LPSPI_FSR_TXCOUNT_MASK (0x7U) 495 #define LPSPI_FSR_TXCOUNT_SHIFT (0U) 496 #define LPSPI_FSR_TXCOUNT_WIDTH (3U) 497 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) 498 499 #define LPSPI_FSR_RXCOUNT_MASK (0x70000U) 500 #define LPSPI_FSR_RXCOUNT_SHIFT (16U) 501 #define LPSPI_FSR_RXCOUNT_WIDTH (3U) 502 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) 503 /*! @} */ 504 505 /*! @name TCR - Transmit Command */ 506 /*! @{ */ 507 508 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) 509 #define LPSPI_TCR_FRAMESZ_SHIFT (0U) 510 #define LPSPI_TCR_FRAMESZ_WIDTH (12U) 511 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) 512 513 #define LPSPI_TCR_WIDTH_MASK (0x30000U) 514 #define LPSPI_TCR_WIDTH_SHIFT (16U) 515 #define LPSPI_TCR_WIDTH_WIDTH (2U) 516 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) 517 518 #define LPSPI_TCR_TXMSK_MASK (0x40000U) 519 #define LPSPI_TCR_TXMSK_SHIFT (18U) 520 #define LPSPI_TCR_TXMSK_WIDTH (1U) 521 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) 522 523 #define LPSPI_TCR_RXMSK_MASK (0x80000U) 524 #define LPSPI_TCR_RXMSK_SHIFT (19U) 525 #define LPSPI_TCR_RXMSK_WIDTH (1U) 526 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) 527 528 #define LPSPI_TCR_CONTC_MASK (0x100000U) 529 #define LPSPI_TCR_CONTC_SHIFT (20U) 530 #define LPSPI_TCR_CONTC_WIDTH (1U) 531 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) 532 533 #define LPSPI_TCR_CONT_MASK (0x200000U) 534 #define LPSPI_TCR_CONT_SHIFT (21U) 535 #define LPSPI_TCR_CONT_WIDTH (1U) 536 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) 537 538 #define LPSPI_TCR_BYSW_MASK (0x400000U) 539 #define LPSPI_TCR_BYSW_SHIFT (22U) 540 #define LPSPI_TCR_BYSW_WIDTH (1U) 541 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) 542 543 #define LPSPI_TCR_LSBF_MASK (0x800000U) 544 #define LPSPI_TCR_LSBF_SHIFT (23U) 545 #define LPSPI_TCR_LSBF_WIDTH (1U) 546 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) 547 548 #define LPSPI_TCR_PCS_MASK (0x7000000U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ 549 #define LPSPI_TCR_PCS_SHIFT (24U) 550 #define LPSPI_TCR_PCS_WIDTH (3U) 551 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ 552 553 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) 554 #define LPSPI_TCR_PRESCALE_SHIFT (27U) 555 #define LPSPI_TCR_PRESCALE_WIDTH (3U) 556 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) 557 558 #define LPSPI_TCR_CPHA_MASK (0x40000000U) 559 #define LPSPI_TCR_CPHA_SHIFT (30U) 560 #define LPSPI_TCR_CPHA_WIDTH (1U) 561 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) 562 563 #define LPSPI_TCR_CPOL_MASK (0x80000000U) 564 #define LPSPI_TCR_CPOL_SHIFT (31U) 565 #define LPSPI_TCR_CPOL_WIDTH (1U) 566 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) 567 /*! @} */ 568 569 /*! @name TDR - Transmit Data */ 570 /*! @{ */ 571 572 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) 573 #define LPSPI_TDR_DATA_SHIFT (0U) 574 #define LPSPI_TDR_DATA_WIDTH (32U) 575 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) 576 /*! @} */ 577 578 /*! @name RSR - Receive Status */ 579 /*! @{ */ 580 581 #define LPSPI_RSR_SOF_MASK (0x1U) 582 #define LPSPI_RSR_SOF_SHIFT (0U) 583 #define LPSPI_RSR_SOF_WIDTH (1U) 584 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) 585 586 #define LPSPI_RSR_RXEMPTY_MASK (0x2U) 587 #define LPSPI_RSR_RXEMPTY_SHIFT (1U) 588 #define LPSPI_RSR_RXEMPTY_WIDTH (1U) 589 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) 590 /*! @} */ 591 592 /*! @name RDR - Receive Data */ 593 /*! @{ */ 594 595 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) 596 #define LPSPI_RDR_DATA_SHIFT (0U) 597 #define LPSPI_RDR_DATA_WIDTH (32U) 598 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) 599 /*! @} */ 600 601 /*! @name RDROR - Receive Data Read Only */ 602 /*! @{ */ 603 604 #define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) 605 #define LPSPI_RDROR_DATA_SHIFT (0U) 606 #define LPSPI_RDROR_DATA_WIDTH (32U) 607 #define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) 608 /*! @} */ 609 610 /*! @name TCBR - Transmit Command Burst */ 611 /*! @{ */ 612 613 #define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) 614 #define LPSPI_TCBR_DATA_SHIFT (0U) 615 #define LPSPI_TCBR_DATA_WIDTH (32U) 616 #define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) 617 /*! @} */ 618 619 /*! @name TDBR - Transmit Data Burst */ 620 /*! @{ */ 621 622 #define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) 623 #define LPSPI_TDBR_DATA_SHIFT (0U) 624 #define LPSPI_TDBR_DATA_WIDTH (32U) 625 #define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) 626 /*! @} */ 627 628 /*! @name RDBR - Receive Data Burst */ 629 /*! @{ */ 630 631 #define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) 632 #define LPSPI_RDBR_DATA_SHIFT (0U) 633 #define LPSPI_RDBR_DATA_WIDTH (32U) 634 #define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) 635 /*! @} */ 636 637 /*! 638 * @} 639 */ /* end of group LPSPI_Register_Masks */ 640 641 /*! 642 * @} 643 */ /* end of group LPSPI_Peripheral_Access_Layer */ 644 645 #endif /* #if !defined(S32K344_LPSPI_H_) */ 646
