IntegerPLL_DIV_CTL_Offset (reference) in projects: hal_nxp-3.7.0

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Searched refs:IntegerPLL_DIV_CTL_Offset (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN5/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN1/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN3/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 815 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 825 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 850 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM6/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 815 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 825 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 850 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN2/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 815 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 825 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 850 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM1/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN4/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN6/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 812 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 822 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 847 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM5/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM4/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM3/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8ML8/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 815 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 825 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 850 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MM2/drivers/
D	fsl_clock.c	`23 #define IntegerPLL_DIV_CTL_Offset (4U) macro 818 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_InitIntegerPll() 828 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) = in CLOCK_InitIntegerPll() 853 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset); in CLOCK_GetIntegerPllFreq()`

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