Searched refs:IRQ_MASK1 (Results 1 – 9 of 9) sorted by relevance
571 base->IRQ_MASK1.SET = (uint32_t)interrupts; in EPDC_EnableLutCompleteInterrupts()584 base->IRQ_MASK1.CLR = (uint32_t)interrupts; in EPDC_DisableLutCompleteInterrupts()597 return (((uint64_t)(base->IRQ_MASK2.RW) << 32U) | (uint64_t)base->IRQ_MASK1.RW); in EPDC_GetEnabledLutCompleteInterrupts()
14487 …__IO uint32_t IRQ_MASK1; /**< EPDC IRQ Mask Register for LUT 0~31, o… member14772 #define EPDC_IRQ_MASK1_REG(base) ((base)->IRQ_MASK1)
14696 } IRQ_MASK1; member
14101 } IRQ_MASK1; member
14098 } IRQ_MASK1; member
