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Searched refs:IP_MC_CGM_6 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2016 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK)… in Clock_Ip_Get_DDR_CLK_Frequency()
2017 …Frequency /= (((IP_MC_CGM_6->MUX_0_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_DDR_CLK_Frequency()
3764 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P6_REG_INTF_CLK_Frequency()
3765 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_P6_REG_INTF_CLK_Frequency()
3766 …Frequency /= (((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHI… in Clock_Ip_Get_P6_REG_INTF_CLK_Frequency()
DClock_Ip_Data.c2748 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_0_CSC),
2749 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_1_CSC),
2828 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_6->PCFS_SDUR)),
/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h217 #define IP_MC_CGM_6 ((MC_CGM_Type *)IP_MC_CGM_6_BASE) macro
221 … { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM_3, IP_MC_CGM_4, IP_MC_CGM_5, IP_MC_CGM_6 }