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Searched refs:IP_MC_CGM_1 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c1736 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency()
1737 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency()
1738 …Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency()
1745 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN3_CLK_Frequency()
1746 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN3_CLK_Frequency()
1747 …Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_LIN3_CLK_Frequency()
1755 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN4_CLK_Frequency()
1756 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN4_CLK_Frequency()
1757 …Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_LIN4_CLK_Frequency()
1765 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN5_CLK_Frequency()
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DClock_Ip_Data.c2656 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_0_CSC),
2657 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_1_CSC),
2658 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_2_CSC),
2659 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_3_CSC),
2660 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_4_CSC),
2661 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_5_CSC),
2662 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_6_CSC),
2663 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_7_CSC),
2664 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_8_CSC),
2665 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_9_CSC),
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/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h197 #define IP_MC_CGM_1 ((MC_CGM_Type *)IP_MC_CGM_1_BASE) macro
221 #define IP_MC_CGM_BASE_PTRS { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM…