1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR6_PCTL.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_GPR6_PCTL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR6_PCTL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR6_PCTL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR6_PCTL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR6_PCTL_Peripheral_Access_Layer GPR6_PCTL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR6_PCTL - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t DDRPCTL; /**< DDRC Clock Control Enable, offset: 0x0 */ 74 } GPR6_PCTL_Type, *GPR6_PCTL_MemMapPtr; 75 76 /** Number of instances of the GPR6_PCTL module. */ 77 #define GPR6_PCTL_INSTANCE_COUNT (1u) 78 79 /* GPR6_PCTL - Peripheral instance base addresses */ 80 /** Peripheral GPR6_PCTL base address */ 81 #define IP_GPR6_PCTL_BASE (0x44010000u) 82 /** Peripheral GPR6_PCTL base pointer */ 83 #define IP_GPR6_PCTL ((GPR6_PCTL_Type *)IP_GPR6_PCTL_BASE) 84 /** Array initializer of GPR6_PCTL peripheral base addresses */ 85 #define IP_GPR6_PCTL_BASE_ADDRS { IP_GPR6_PCTL_BASE } 86 /** Array initializer of GPR6_PCTL peripheral base pointers */ 87 #define IP_GPR6_PCTL_BASE_PTRS { IP_GPR6_PCTL } 88 89 /* ---------------------------------------------------------------------------- 90 -- GPR6_PCTL Register Masks 91 ---------------------------------------------------------------------------- */ 92 93 /*! 94 * @addtogroup GPR6_PCTL_Register_Masks GPR6_PCTL Register Masks 95 * @{ 96 */ 97 98 /*! @name DDRPCTL - DDRC Clock Control Enable */ 99 /*! @{ */ 100 101 #define GPR6_PCTL_DDRPCTL_PCTL_MASK (0x1U) 102 #define GPR6_PCTL_DDRPCTL_PCTL_SHIFT (0U) 103 #define GPR6_PCTL_DDRPCTL_PCTL_WIDTH (1U) 104 #define GPR6_PCTL_DDRPCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR6_PCTL_DDRPCTL_PCTL_SHIFT)) & GPR6_PCTL_DDRPCTL_PCTL_MASK) 105 /*! @} */ 106 107 /*! 108 * @} 109 */ /* end of group GPR6_PCTL_Register_Masks */ 110 111 /*! 112 * @} 113 */ /* end of group GPR6_PCTL_Peripheral_Access_Layer */ 114 115 #endif /* #if !defined(S32Z2_GPR6_PCTL_H_) */ 116
