Searched refs:IP_CORE_PLL (Results 1 – 4 of 4) sorted by relevance
259 if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if CORE_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()261 …IP_CORE_PLL->PLLCLKMUX = 0U; /* FIRC input refer… in Clock_Ip_SpecificPlatformInitClock()262 RegValue = IP_CORE_PLL->PLLDV; in Clock_Ip_SpecificPlatformInitClock()264 …IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) ); /* /1… in Clock_Ip_SpecificPlatformInitClock()266 …IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modulati… in Clock_Ip_SpecificPlatformInitClock()267 …IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start CORE_PLL */ in Clock_Ip_SpecificPlatformInitClock()303 if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if CORE_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()305 …IP_CORE_PLL->PLLCLKMUX = 0U; /* FIRC input refer… in Clock_Ip_SpecificPlatformInitClock()306 RegValue = IP_CORE_PLL->PLLDV; in Clock_Ip_SpecificPlatformInitClock()308 …IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) ); /* /1… in Clock_Ip_SpecificPlatformInitClock()[all …]
1384 …if (Clock_Ip_u32CorePllChecksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLL… in Clock_Ip_Get_COREPLL_CLK_Frequency()1386 … Clock_Ip_u32CorePllChecksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD); in Clock_Ip_Get_COREPLL_CLK_Frequency()1387 Clock_Ip_u32CorePllFreq = PLL_VCO(IP_CORE_PLL); in Clock_Ip_Get_COREPLL_CLK_Frequency()1389 …return (((IP_CORE_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_… in Clock_Ip_Get_COREPLL_CLK_Frequency()1415 …Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PL… in Clock_Ip_Get_COREPLL_PHI0_Frequency()1416 …Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) +… in Clock_Ip_Get_COREPLL_PHI0_Frequency()1423 …if (Clock_Ip_u32CoreDfs1Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PL… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1425 …Clock_Ip_u32CoreDfs1Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1433 …if (Clock_Ip_u32CoreDfs2Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PL… in Clock_Ip_Get_COREPLL_DFS1_Frequency()1435 …Clock_Ip_u32CoreDfs2Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^… in Clock_Ip_Get_COREPLL_DFS1_Frequency()[all …]
2904 IP_CORE_PLL,
94 #define IP_CORE_PLL ((PLLDIG_Type *)IP_CORE_PLL_BASE) macro106 #define IP_PLLDIG_BASE_PTRS { IP_CORE_PLL, IP_DDR_PLL, IP_PERIPH_PLL }
