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Searched refs:IPRXFCR (Results 1 – 25 of 100) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi_edma.c194 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_TransferEDMA()
249 …handle->count = (uint8_t)((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_… in FLEXSPI_TransferEDMA()
325 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortEDMA()
347 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountEDMA()
Dfsl_flexspi.c344 base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; in FLEXSPI_Init()
345 base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U); in FLEXSPI_Init()
733 …uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SH… in FLEXSPI_ReadBlocking()
853 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_TransferBlocking()
977 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_TransferNonBlocking()
1093 …rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U; in FLEXSPI_TransferHandleIRQ()
Dfsl_flexspi_dma.c328 …8U * (uint8_t)(((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1… in FLEXSPI_ReadDataDMA()
545 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_TransferDMA()
607 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortDMA()
629 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountDMA()
Dfsl_flexspi.h518 base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; in FLEXSPI_EnableRxDMA()
522 base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; in FLEXSPI_EnableRxDMA()
567 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_ResetFifos()
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/flexspi/flexspi_dma3/
Dfsl_flexspi_edma.c210 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; in FLEXSPI_TransferEDMA()
265 …handle->count = (uint8_t)((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_… in FLEXSPI_TransferEDMA()
341 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortEDMA()
363 if ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountEDMA()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7155 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
DMIMXRT685S_cm33.h13132 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13523 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h15932 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13132 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h13456 __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13001 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h13456 __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19271 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19251 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21380 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20228 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h21757 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21013 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21382 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h19595 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h13455 __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h22543 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h26870 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h26868 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ member

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