| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/flexspi/ |
| D | fsl_flexspi.h | 714 base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; in FLEXSPI_EnableIPParallelMode()
718 base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; in FLEXSPI_EnableIPParallelMode()
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| D | fsl_flexspi_edma.c | 204 base->IPCR1 = configValue; in FLEXSPI_TransferEDMA()
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| D | fsl_flexspi.c | 864 base->IPCR1 = configValue; in FLEXSPI_TransferBlocking()
988 base->IPCR1 = configValue; in FLEXSPI_TransferNonBlocking()
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| D | fsl_flexspi_dma.c | 555 base->IPCR1 = configValue; in FLEXSPI_TransferDMA()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/flexspi/flexspi_dma3/ |
| D | fsl_flexspi_edma.c | 220 base->IPCR1 = configValue; in FLEXSPI_TransferEDMA()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/semc/ |
| D | fsl_semc.c | 241 base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); in SEMC_ConfigureIPCommand()
517 SEMC->IPCR1 = 0x2U; in SEMC_ConfigureSDRAM()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 315 MEM_WriteU32(0x400d4094, 0x00000002); // IPCR1
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| /hal_nxp-3.7.0/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 315 MEM_WriteU32(0x400d4094, 0x00000002); // IPCR1
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 19267 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
33260 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 19247 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
33239 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 21376 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
36038 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 20224 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
34823 …__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 21753 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
36922 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 21009 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
39089 …__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 21378 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
39448 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 22539 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
41116 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 22612 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
41123 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 7151 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 13519 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 15928 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 36754 __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ member
64065 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm7.h | 36754 __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ member
64065 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| D | MIMXRT1175_cm4.h | 36751 __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ member
64967 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm7.h | 36442 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
63563 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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| D | MIMXRT1165_cm4.h | 36439 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ member
64465 …__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 … member
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