| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/qspi/ |
| D | fsl_qspi.h | 292 __IO uint32_t IPCR; /*!< IP Configuration Register */ member
546 command.commandRegBase = &(base->IPCR); in QSPI_SetIPCommandSize()
576 base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK; in QSPI_EnableIPParallelMode()
580 base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK; in QSPI_EnableIPParallelMode()
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| D | fsl_qspi.c | 408 base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / 4U)); in QSPI_ExecuteIPCommand()
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| /hal_nxp-3.7.0/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_QUADSPI.h | 79 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_QUADSPI.h | 79 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HwAccess.h | 60 BaseAddr->IPCR = QuadSPI_IPCR_SEQID(SeqID) in Qspi_Ip_IpTrigger()
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| /hal_nxp-3.7.0/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 2011 BaseAddr->IPCR = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
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| /hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 81 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK80F25615/ |
| D | MK80F25615.h | 18257 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 19230 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 30416 …__IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8… member
30467 #define QuadSPI_IPCR_REG(base) ((base)->IPCR)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK27FA15/ |
| D | MK27FA15.h | 17759 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MK28FA15/ |
| D | MK28FA15.h | 17761 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 37614 …__IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8… member
37665 #define QuadSPI_IPCR_REG(base) ((base)->IPCR)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 25100 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 25101 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 43990 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 46163 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46163 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46163 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 46163 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ member
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