Searched refs:IMR1 (Results 1 – 4 of 4) sorted by relevance
419 base->IMR1 &= ~((interruptMask >> 2UL) & 0x3UL); in ACOMP_EnableInterrupts()432 base->IMR1 |= ((interruptMask >> 2UL) & 0x3UL); in ACOMP_DisableInterrupt()
13474 __IO uint32_t IMR1; /**< IRQ masking register 1, offset: 0x8 */ member13499 #define GPC_IMR1_REG(base) ((base)->IMR1)
269 …__IO uint32_t IMR1; /**< ACOMP1 Interrupt Mask Register, offset: 0x24… member
