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Searched refs:HPSR (Results 1 – 25 of 55) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/snvs_hp/
Dfsl_snvs_hp.h320 base->HPSR |= mask; in SNVS_HP_RTC_ClearStatusFlags()
443 …return (snvs_hp_ssm_state_t)((uint32_t)((base->HPSR & SNVS_HPSR_SSM_STATE_MASK) >> SNVS_HPSR_SSM_S… in SNVS_HP_GetSSMState()
576 return base->HPSR; in SNVS_HP_GetStatusFlags()
593 base->HPSR = mask; in SNVS_HP_ClearStatusFlags()
Dfsl_snvs_hp.c505 if ((base->HPSR & SNVS_HPSR_PI_MASK) != 0U) in SNVS_HP_RTC_GetStatusFlags()
510 if ((base->HPSR & SNVS_HPSR_HPTA_MASK) != 0U) in SNVS_HP_RTC_GetStatusFlags()
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/snvs_lp/
Dfsl_snvs_lp.c1328 … uint32_t curr_ssm_state = ((base->HPSR & SNVS_HPSR_SSM_STATE_MASK) >> SNVS_HPSR_SSM_STATE_SHIFT); in SNVS_LP_SSM_State_Transition()
1347 uint32_t new_ssm_state = ((base->HPSR & SNVS_HPSR_SSM_STATE_MASK) >> SNVS_HPSR_SSM_STATE_SHIFT); in SNVS_LP_SSM_State_Transition()
/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h33412 __IO uint32_t HPSR; /**< , offset: 0x14 */ member
33445 #define SNVS_HPSR_REG(base) ((base)->HPSR)
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h40148 __IO uint32_t HPSR; /**< , offset: 0x14 */ member
40181 #define SNVS_HPSR_REG(base) ((base)->HPSR)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h27038 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h29169 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h29747 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h29748 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h34469 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h34448 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h37459 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h36019 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h38343 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h40285 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h40869 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h42537 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h48978 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h47781 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h47779 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h47781 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h47793 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
DMIMX8MN6_cm7.h47779 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h47779 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h47781 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ member

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