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Searched refs:HOST_CTRL_CAP (Results 1 – 25 of 102) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/usdhc/
Dfsl_usdhc.h1336 … return ((base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) != 0UL) ? true : false; in USDHC_RequestTuningForSDR50()
1378 base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; in USDHC_SetRetuningTimer()
1379 base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); in USDHC_SetRetuningTimer()
Dfsl_usdhc.c949 htCapability = base->HOST_CTRL_CAP; in USDHC_GetCapability()
/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_USDHC.h89 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h20471 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
DK32L3A60_cm4.h20421 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h40294 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: … member
40338 #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h31869 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
DMIMXRT685S_cm33.h42821 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h43903 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: … member
43950 #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h35862 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h35863 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h42821 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h47526 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h41969 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h41948 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h45030 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h44029 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h46421 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h48295 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h48440 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h56936 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h50615 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h54529 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h53260 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h53258 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member

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