1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR5.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_GPR5 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR5_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR5_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR5 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR5_Peripheral_Access_Layer GPR5 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR5 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD5; /**< VFCCU Global DID register 5, offset: 0x0 */ 74 __IO uint32_t LVFCCULD15; /**< VFCCU Local DID register 15, offset: 0x4 */ 75 __IO uint32_t LVFCCULD16; /**< VFCCU Local DID register 16, offset: 0x8 */ 76 __IO uint32_t LVFCCULD17; /**< VFCCU Local DID register 17, offset: 0xC */ 77 uint8_t RESERVED_0[52]; 78 __I uint32_t INITM5; /**< NoC Initiator NIU Timeout Status, offset: 0x44 */ 79 __I uint32_t TARGTMS5; /**< NoC Target NIU Timeout Status, offset: 0x48 */ 80 __IO uint32_t TARGTMC5; /**< NoC Target NIU Timeout Control, offset: 0x4C */ 81 uint8_t RESERVED_1[4]; 82 __IO uint32_t CLKOUT3SEL; /**< CLKOUT_3 MUX select, offset: 0x54 */ 83 uint8_t RESERVED_2[20]; 84 __IO uint32_t LVFCCU5S; /**< VFCCU Fault Status 5, offset: 0x6C */ 85 } GPR5_Type, *GPR5_MemMapPtr; 86 87 /** Number of instances of the GPR5 module. */ 88 #define GPR5_INSTANCE_COUNT (1u) 89 90 /* GPR5 - Peripheral instance base addresses */ 91 /** Peripheral GPR5 base address */ 92 #define IP_GPR5_BASE (0x42860000u) 93 /** Peripheral GPR5 base pointer */ 94 #define IP_GPR5 ((GPR5_Type *)IP_GPR5_BASE) 95 /** Array initializer of GPR5 peripheral base addresses */ 96 #define IP_GPR5_BASE_ADDRS { IP_GPR5_BASE } 97 /** Array initializer of GPR5 peripheral base pointers */ 98 #define IP_GPR5_BASE_PTRS { IP_GPR5 } 99 100 /* ---------------------------------------------------------------------------- 101 -- GPR5 Register Masks 102 ---------------------------------------------------------------------------- */ 103 104 /*! 105 * @addtogroup GPR5_Register_Masks GPR5 Register Masks 106 * @{ 107 */ 108 109 /*! @name LVFCCUGD5 - VFCCU Global DID register 5 */ 110 /*! @{ */ 111 112 #define GPR5_LVFCCUGD5_FHID_MASK (0xFU) 113 #define GPR5_LVFCCUGD5_FHID_SHIFT (0U) 114 #define GPR5_LVFCCUGD5_FHID_WIDTH (4U) 115 #define GPR5_LVFCCUGD5_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR5_LVFCCUGD5_FHID_SHIFT)) & GPR5_LVFCCUGD5_FHID_MASK) 116 /*! @} */ 117 118 /*! @name LVFCCULD15 - VFCCU Local DID register 15 */ 119 /*! @{ */ 120 121 #define GPR5_LVFCCULD15_FHID_MASK (0xFFFFFFFFU) 122 #define GPR5_LVFCCULD15_FHID_SHIFT (0U) 123 #define GPR5_LVFCCULD15_FHID_WIDTH (32U) 124 #define GPR5_LVFCCULD15_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR5_LVFCCULD15_FHID_SHIFT)) & GPR5_LVFCCULD15_FHID_MASK) 125 /*! @} */ 126 127 /*! @name LVFCCULD16 - VFCCU Local DID register 16 */ 128 /*! @{ */ 129 130 #define GPR5_LVFCCULD16_FHID_MASK (0xFFFFFFFFU) 131 #define GPR5_LVFCCULD16_FHID_SHIFT (0U) 132 #define GPR5_LVFCCULD16_FHID_WIDTH (32U) 133 #define GPR5_LVFCCULD16_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR5_LVFCCULD16_FHID_SHIFT)) & GPR5_LVFCCULD16_FHID_MASK) 134 /*! @} */ 135 136 /*! @name LVFCCULD17 - VFCCU Local DID register 17 */ 137 /*! @{ */ 138 139 #define GPR5_LVFCCULD17_FHID_MASK (0xFFFFFFFFU) 140 #define GPR5_LVFCCULD17_FHID_SHIFT (0U) 141 #define GPR5_LVFCCULD17_FHID_WIDTH (32U) 142 #define GPR5_LVFCCULD17_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR5_LVFCCULD17_FHID_SHIFT)) & GPR5_LVFCCULD17_FHID_MASK) 143 /*! @} */ 144 145 /*! @name INITM5 - NoC Initiator NIU Timeout Status */ 146 /*! @{ */ 147 148 #define GPR5_INITM5_STAT_MASK (0xFFFFFFFFU) 149 #define GPR5_INITM5_STAT_SHIFT (0U) 150 #define GPR5_INITM5_STAT_WIDTH (32U) 151 #define GPR5_INITM5_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR5_INITM5_STAT_SHIFT)) & GPR5_INITM5_STAT_MASK) 152 /*! @} */ 153 154 /*! @name TARGTMS5 - NoC Target NIU Timeout Status */ 155 /*! @{ */ 156 157 #define GPR5_TARGTMS5_STAT_MASK (0xFFFFFFFFU) 158 #define GPR5_TARGTMS5_STAT_SHIFT (0U) 159 #define GPR5_TARGTMS5_STAT_WIDTH (32U) 160 #define GPR5_TARGTMS5_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR5_TARGTMS5_STAT_SHIFT)) & GPR5_TARGTMS5_STAT_MASK) 161 /*! @} */ 162 163 /*! @name TARGTMC5 - NoC Target NIU Timeout Control */ 164 /*! @{ */ 165 166 #define GPR5_TARGTMC5_EN_MASK (0xFFFFFFFFU) 167 #define GPR5_TARGTMC5_EN_SHIFT (0U) 168 #define GPR5_TARGTMC5_EN_WIDTH (32U) 169 #define GPR5_TARGTMC5_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR5_TARGTMC5_EN_SHIFT)) & GPR5_TARGTMC5_EN_MASK) 170 /*! @} */ 171 172 /*! @name CLKOUT3SEL - CLKOUT_3 MUX select */ 173 /*! @{ */ 174 175 #define GPR5_CLKOUT3SEL_MUXSEL_MASK (0xFU) 176 #define GPR5_CLKOUT3SEL_MUXSEL_SHIFT (0U) 177 #define GPR5_CLKOUT3SEL_MUXSEL_WIDTH (4U) 178 #define GPR5_CLKOUT3SEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_CLKOUT3SEL_MUXSEL_SHIFT)) & GPR5_CLKOUT3SEL_MUXSEL_MASK) 179 /*! @} */ 180 181 /*! @name LVFCCU5S - VFCCU Fault Status 5 */ 182 /*! @{ */ 183 184 #define GPR5_LVFCCU5S_STAT_MASK (0xFFFFFFFFU) 185 #define GPR5_LVFCCU5S_STAT_SHIFT (0U) 186 #define GPR5_LVFCCU5S_STAT_WIDTH (32U) 187 #define GPR5_LVFCCU5S_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR5_LVFCCU5S_STAT_SHIFT)) & GPR5_LVFCCU5S_STAT_MASK) 188 /*! @} */ 189 190 /*! 191 * @} 192 */ /* end of group GPR5_Register_Masks */ 193 194 /*! 195 * @} 196 */ /* end of group GPR5_Peripheral_Access_Layer */ 197 198 #endif /* #if !defined(S32Z2_GPR5_H_) */ 199
