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Searched refs:GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR5_PCTL.h122 #define GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK (0x8U) macro
125 …(uint32_t)(((uint32_t)(x)) << GPR5_PCTL_EDMA5PCTL_PCTL_3_SHIFT)) & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK)
/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3810 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK) >… in Clock_Ip_Get_PIT5_CLK_Frequency()