1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR1.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_GPR1 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR1_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR1_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR1 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR1_Peripheral_Access_Layer GPR1 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR1 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD1; /**< VFCCU Global DID register 1, offset: 0x0 */ 74 __IO uint32_t LVFCCULD3; /**< VFCCU Local DID register 3, offset: 0x4 */ 75 __IO uint32_t LVFCCULD4; /**< VFCCU Local DID register 4, offset: 0x8 */ 76 __IO uint32_t LVFCCULD5; /**< VFCCU Local DID register 5, offset: 0xC */ 77 uint8_t RESERVED_0[36]; 78 __IO uint32_t FUNCC2; /**< Functional Reset Control register 2, offset: 0x34 */ 79 uint8_t RESERVED_1[12]; 80 __I uint32_t INITM1; /**< NoC Initiator NIU Timeout Status, offset: 0x44 */ 81 __I uint32_t TARGTMS1; /**< NoC Target NIU Timeout Status, offset: 0x48 */ 82 __IO uint32_t TARGTMC1; /**< NoC Target NIU Timeout Control, offset: 0x4C */ 83 uint8_t RESERVED_2[4]; 84 __IO uint32_t NETCC0; /**< NETC Control register 0, offset: 0x54 */ 85 __IO uint32_t NETCC1; /**< NETC Control register 1, offset: 0x58 */ 86 __IO uint32_t CLKOUT1SEL; /**< CLKOUT_1 MUX select, offset: 0x5C */ 87 uint8_t RESERVED_3[16]; 88 __IO uint32_t LVFCCU1S; /**< VFCCU Fault Status 1, offset: 0x70 */ 89 __IO uint32_t XPAR1; /**< Interface parity control and status register, offset: 0x74 */ 90 } GPR1_Type, *GPR1_MemMapPtr; 91 92 /** Number of instances of the GPR1 module. */ 93 #define GPR1_INSTANCE_COUNT (1u) 94 95 /* GPR1 - Peripheral instance base addresses */ 96 /** Peripheral GPR1 base address */ 97 #define IP_GPR1_BASE (0x40860000u) 98 /** Peripheral GPR1 base pointer */ 99 #define IP_GPR1 ((GPR1_Type *)IP_GPR1_BASE) 100 /** Array initializer of GPR1 peripheral base addresses */ 101 #define IP_GPR1_BASE_ADDRS { IP_GPR1_BASE } 102 /** Array initializer of GPR1 peripheral base pointers */ 103 #define IP_GPR1_BASE_PTRS { IP_GPR1 } 104 105 /* ---------------------------------------------------------------------------- 106 -- GPR1 Register Masks 107 ---------------------------------------------------------------------------- */ 108 109 /*! 110 * @addtogroup GPR1_Register_Masks GPR1 Register Masks 111 * @{ 112 */ 113 114 /*! @name LVFCCUGD1 - VFCCU Global DID register 1 */ 115 /*! @{ */ 116 117 #define GPR1_LVFCCUGD1_FHID_MASK (0xFU) 118 #define GPR1_LVFCCUGD1_FHID_SHIFT (0U) 119 #define GPR1_LVFCCUGD1_FHID_WIDTH (4U) 120 #define GPR1_LVFCCUGD1_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR1_LVFCCUGD1_FHID_SHIFT)) & GPR1_LVFCCUGD1_FHID_MASK) 121 /*! @} */ 122 123 /*! @name LVFCCULD3 - VFCCU Local DID register 3 */ 124 /*! @{ */ 125 126 #define GPR1_LVFCCULD3_FHID_MASK (0xFFFFFFFFU) 127 #define GPR1_LVFCCULD3_FHID_SHIFT (0U) 128 #define GPR1_LVFCCULD3_FHID_WIDTH (32U) 129 #define GPR1_LVFCCULD3_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR1_LVFCCULD3_FHID_SHIFT)) & GPR1_LVFCCULD3_FHID_MASK) 130 /*! @} */ 131 132 /*! @name LVFCCULD4 - VFCCU Local DID register 4 */ 133 /*! @{ */ 134 135 #define GPR1_LVFCCULD4_FHID_MASK (0xFFFFFFFFU) 136 #define GPR1_LVFCCULD4_FHID_SHIFT (0U) 137 #define GPR1_LVFCCULD4_FHID_WIDTH (32U) 138 #define GPR1_LVFCCULD4_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR1_LVFCCULD4_FHID_SHIFT)) & GPR1_LVFCCULD4_FHID_MASK) 139 /*! @} */ 140 141 /*! @name LVFCCULD5 - VFCCU Local DID register 5 */ 142 /*! @{ */ 143 144 #define GPR1_LVFCCULD5_FHID_MASK (0xFFFFFFFFU) 145 #define GPR1_LVFCCULD5_FHID_SHIFT (0U) 146 #define GPR1_LVFCCULD5_FHID_WIDTH (32U) 147 #define GPR1_LVFCCULD5_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR1_LVFCCULD5_FHID_SHIFT)) & GPR1_LVFCCULD5_FHID_MASK) 148 /*! @} */ 149 150 /*! @name FUNCC2 - Functional Reset Control register 2 */ 151 /*! @{ */ 152 153 #define GPR1_FUNCC2_CTRL_MASK (0xFFFFFFFFU) 154 #define GPR1_FUNCC2_CTRL_SHIFT (0U) 155 #define GPR1_FUNCC2_CTRL_WIDTH (32U) 156 #define GPR1_FUNCC2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_FUNCC2_CTRL_SHIFT)) & GPR1_FUNCC2_CTRL_MASK) 157 /*! @} */ 158 159 /*! @name INITM1 - NoC Initiator NIU Timeout Status */ 160 /*! @{ */ 161 162 #define GPR1_INITM1_STAT_MASK (0xFFFFFFFFU) 163 #define GPR1_INITM1_STAT_SHIFT (0U) 164 #define GPR1_INITM1_STAT_WIDTH (32U) 165 #define GPR1_INITM1_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR1_INITM1_STAT_SHIFT)) & GPR1_INITM1_STAT_MASK) 166 /*! @} */ 167 168 /*! @name TARGTMS1 - NoC Target NIU Timeout Status */ 169 /*! @{ */ 170 171 #define GPR1_TARGTMS1_STAT_MASK (0xFFFFFFFFU) 172 #define GPR1_TARGTMS1_STAT_SHIFT (0U) 173 #define GPR1_TARGTMS1_STAT_WIDTH (32U) 174 #define GPR1_TARGTMS1_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR1_TARGTMS1_STAT_SHIFT)) & GPR1_TARGTMS1_STAT_MASK) 175 /*! @} */ 176 177 /*! @name TARGTMC1 - NoC Target NIU Timeout Control */ 178 /*! @{ */ 179 180 #define GPR1_TARGTMC1_EN_MASK (0xFFFFFFFFU) 181 #define GPR1_TARGTMC1_EN_SHIFT (0U) 182 #define GPR1_TARGTMC1_EN_WIDTH (32U) 183 #define GPR1_TARGTMC1_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR1_TARGTMC1_EN_SHIFT)) & GPR1_TARGTMC1_EN_MASK) 184 /*! @} */ 185 186 /*! @name NETCC0 - NETC Control register 0 */ 187 /*! @{ */ 188 189 #define GPR1_NETCC0_IERBLOCK_MASK (0x1U) 190 #define GPR1_NETCC0_IERBLOCK_SHIFT (0U) 191 #define GPR1_NETCC0_IERBLOCK_WIDTH (1U) 192 #define GPR1_NETCC0_IERBLOCK(x) (((uint32_t)(((uint32_t)(x)) << GPR1_NETCC0_IERBLOCK_SHIFT)) & GPR1_NETCC0_IERBLOCK_MASK) 193 /*! @} */ 194 195 /*! @name NETCC1 - NETC Control register 1 */ 196 /*! @{ */ 197 198 #define GPR1_NETCC1_LINK0MIIP_MASK (0xFU) 199 #define GPR1_NETCC1_LINK0MIIP_SHIFT (0U) 200 #define GPR1_NETCC1_LINK0MIIP_WIDTH (4U) 201 #define GPR1_NETCC1_LINK0MIIP(x) (((uint32_t)(((uint32_t)(x)) << GPR1_NETCC1_LINK0MIIP_SHIFT)) & GPR1_NETCC1_LINK0MIIP_MASK) 202 203 #define GPR1_NETCC1_LINK1MIIP_MASK (0xF0U) 204 #define GPR1_NETCC1_LINK1MIIP_SHIFT (4U) 205 #define GPR1_NETCC1_LINK1MIIP_WIDTH (4U) 206 #define GPR1_NETCC1_LINK1MIIP(x) (((uint32_t)(((uint32_t)(x)) << GPR1_NETCC1_LINK1MIIP_SHIFT)) & GPR1_NETCC1_LINK1MIIP_MASK) 207 /*! @} */ 208 209 /*! @name CLKOUT1SEL - CLKOUT_1 MUX select */ 210 /*! @{ */ 211 212 #define GPR1_CLKOUT1SEL_MUXSEL_MASK (0x3FU) 213 #define GPR1_CLKOUT1SEL_MUXSEL_SHIFT (0U) 214 #define GPR1_CLKOUT1SEL_MUXSEL_WIDTH (6U) 215 #define GPR1_CLKOUT1SEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_CLKOUT1SEL_MUXSEL_SHIFT)) & GPR1_CLKOUT1SEL_MUXSEL_MASK) 216 /*! @} */ 217 218 /*! @name LVFCCU1S - VFCCU Fault Status 1 */ 219 /*! @{ */ 220 221 #define GPR1_LVFCCU1S_STAT_MASK (0xFFFFFFFFU) 222 #define GPR1_LVFCCU1S_STAT_SHIFT (0U) 223 #define GPR1_LVFCCU1S_STAT_WIDTH (32U) 224 #define GPR1_LVFCCU1S_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR1_LVFCCU1S_STAT_SHIFT)) & GPR1_LVFCCU1S_STAT_MASK) 225 /*! @} */ 226 227 /*! @name XPAR1 - Interface parity control and status register */ 228 /*! @{ */ 229 230 #define GPR1_XPAR1_DIS_MASK (0x1U) 231 #define GPR1_XPAR1_DIS_SHIFT (0U) 232 #define GPR1_XPAR1_DIS_WIDTH (1U) 233 #define GPR1_XPAR1_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR1_XPAR1_DIS_SHIFT)) & GPR1_XPAR1_DIS_MASK) 234 235 #define GPR1_XPAR1_STAT_MASK (0x100U) 236 #define GPR1_XPAR1_STAT_SHIFT (8U) 237 #define GPR1_XPAR1_STAT_WIDTH (1U) 238 #define GPR1_XPAR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR1_XPAR1_STAT_SHIFT)) & GPR1_XPAR1_STAT_MASK) 239 /*! @} */ 240 241 /*! 242 * @} 243 */ /* end of group GPR1_Register_Masks */ 244 245 /*! 246 * @} 247 */ /* end of group GPR1_Peripheral_Access_Layer */ 248 249 #endif /* #if !defined(S32Z2_GPR1_H_) */ 250
