1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR0.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_GPR0 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR0_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR0_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR0 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR0_Peripheral_Access_Layer GPR0 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR0 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD0; /**< VFCCU Global DID register 0, offset: 0x0 */ 74 __IO uint32_t LVFCCULD0; /**< VFCCU Local DID register 0, offset: 0x4 */ 75 __IO uint32_t LVFCCULD1; /**< VFCCU Local DID register 1, offset: 0x8 */ 76 __IO uint32_t LVFCCULD2; /**< VFCCU Local DID register 2, offset: 0xC */ 77 __IO uint32_t FROSTICKC; /**< FlexRay OS Tick Mux Selector, offset: 0x10 */ 78 uint8_t RESERVED_0[52]; 79 __I uint32_t INITM0; /**< NoC Initiator NIU Timeout Status, offset: 0x48 */ 80 __I uint32_t TARGTMS0; /**< NoC Target NIU Timeout Status, offset: 0x4C */ 81 __IO uint32_t TARGTMC0; /**< NoC Target NIU Timeout Control, offset: 0x50 */ 82 uint8_t RESERVED_1[4]; 83 __IO uint32_t CLKOUT0SEL; /**< CLKOUT_0 MUX select, offset: 0x58 */ 84 uint8_t RESERVED_2[20]; 85 __IO uint32_t LVFCCU0S; /**< VFCCU Fault Status 0, offset: 0x70 */ 86 } GPR0_Type, *GPR0_MemMapPtr; 87 88 /** Number of instances of the GPR0 module. */ 89 #define GPR0_INSTANCE_COUNT (1u) 90 91 /* GPR0 - Peripheral instance base addresses */ 92 /** Peripheral GPR0 base address */ 93 #define IP_GPR0_BASE (0x40060000u) 94 /** Peripheral GPR0 base pointer */ 95 #define IP_GPR0 ((GPR0_Type *)IP_GPR0_BASE) 96 /** Array initializer of GPR0 peripheral base addresses */ 97 #define IP_GPR0_BASE_ADDRS { IP_GPR0_BASE } 98 /** Array initializer of GPR0 peripheral base pointers */ 99 #define IP_GPR0_BASE_PTRS { IP_GPR0 } 100 101 /* ---------------------------------------------------------------------------- 102 -- GPR0 Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup GPR0_Register_Masks GPR0 Register Masks 107 * @{ 108 */ 109 110 /*! @name LVFCCUGD0 - VFCCU Global DID register 0 */ 111 /*! @{ */ 112 113 #define GPR0_LVFCCUGD0_FHID_MASK (0xFU) 114 #define GPR0_LVFCCUGD0_FHID_SHIFT (0U) 115 #define GPR0_LVFCCUGD0_FHID_WIDTH (4U) 116 #define GPR0_LVFCCUGD0_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR0_LVFCCUGD0_FHID_SHIFT)) & GPR0_LVFCCUGD0_FHID_MASK) 117 /*! @} */ 118 119 /*! @name LVFCCULD0 - VFCCU Local DID register 0 */ 120 /*! @{ */ 121 122 #define GPR0_LVFCCULD0_FHID_MASK (0xFFFFFFFFU) 123 #define GPR0_LVFCCULD0_FHID_SHIFT (0U) 124 #define GPR0_LVFCCULD0_FHID_WIDTH (32U) 125 #define GPR0_LVFCCULD0_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR0_LVFCCULD0_FHID_SHIFT)) & GPR0_LVFCCULD0_FHID_MASK) 126 /*! @} */ 127 128 /*! @name LVFCCULD1 - VFCCU Local DID register 1 */ 129 /*! @{ */ 130 131 #define GPR0_LVFCCULD1_FHID_MASK (0xFFFFFFFFU) 132 #define GPR0_LVFCCULD1_FHID_SHIFT (0U) 133 #define GPR0_LVFCCULD1_FHID_WIDTH (32U) 134 #define GPR0_LVFCCULD1_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR0_LVFCCULD1_FHID_SHIFT)) & GPR0_LVFCCULD1_FHID_MASK) 135 /*! @} */ 136 137 /*! @name LVFCCULD2 - VFCCU Local DID register 2 */ 138 /*! @{ */ 139 140 #define GPR0_LVFCCULD2_FHID_MASK (0xFFFFFFFFU) 141 #define GPR0_LVFCCULD2_FHID_SHIFT (0U) 142 #define GPR0_LVFCCULD2_FHID_WIDTH (32U) 143 #define GPR0_LVFCCULD2_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR0_LVFCCULD2_FHID_SHIFT)) & GPR0_LVFCCULD2_FHID_MASK) 144 /*! @} */ 145 146 /*! @name FROSTICKC - FlexRay OS Tick Mux Selector */ 147 /*! @{ */ 148 149 #define GPR0_FROSTICKC_SEL_MASK (0x3U) 150 #define GPR0_FROSTICKC_SEL_SHIFT (0U) 151 #define GPR0_FROSTICKC_SEL_WIDTH (2U) 152 #define GPR0_FROSTICKC_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPR0_FROSTICKC_SEL_SHIFT)) & GPR0_FROSTICKC_SEL_MASK) 153 /*! @} */ 154 155 /*! @name INITM0 - NoC Initiator NIU Timeout Status */ 156 /*! @{ */ 157 158 #define GPR0_INITM0_STAT_MASK (0xFFFFFFFFU) 159 #define GPR0_INITM0_STAT_SHIFT (0U) 160 #define GPR0_INITM0_STAT_WIDTH (32U) 161 #define GPR0_INITM0_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR0_INITM0_STAT_SHIFT)) & GPR0_INITM0_STAT_MASK) 162 /*! @} */ 163 164 /*! @name TARGTMS0 - NoC Target NIU Timeout Status */ 165 /*! @{ */ 166 167 #define GPR0_TARGTMS0_STAT_MASK (0xFFFFFFFFU) 168 #define GPR0_TARGTMS0_STAT_SHIFT (0U) 169 #define GPR0_TARGTMS0_STAT_WIDTH (32U) 170 #define GPR0_TARGTMS0_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR0_TARGTMS0_STAT_SHIFT)) & GPR0_TARGTMS0_STAT_MASK) 171 /*! @} */ 172 173 /*! @name TARGTMC0 - NoC Target NIU Timeout Control */ 174 /*! @{ */ 175 176 #define GPR0_TARGTMC0_EN_MASK (0xFFFFFFFFU) 177 #define GPR0_TARGTMC0_EN_SHIFT (0U) 178 #define GPR0_TARGTMC0_EN_WIDTH (32U) 179 #define GPR0_TARGTMC0_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR0_TARGTMC0_EN_SHIFT)) & GPR0_TARGTMC0_EN_MASK) 180 /*! @} */ 181 182 /*! @name CLKOUT0SEL - CLKOUT_0 MUX select */ 183 /*! @{ */ 184 185 #define GPR0_CLKOUT0SEL_MUXSEL_MASK (0x3FU) 186 #define GPR0_CLKOUT0SEL_MUXSEL_SHIFT (0U) 187 #define GPR0_CLKOUT0SEL_MUXSEL_WIDTH (6U) 188 #define GPR0_CLKOUT0SEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << GPR0_CLKOUT0SEL_MUXSEL_SHIFT)) & GPR0_CLKOUT0SEL_MUXSEL_MASK) 189 190 #define GPR0_CLKOUT0SEL_CGEN_MASK (0x40U) 191 #define GPR0_CLKOUT0SEL_CGEN_SHIFT (6U) 192 #define GPR0_CLKOUT0SEL_CGEN_WIDTH (1U) 193 #define GPR0_CLKOUT0SEL_CGEN(x) (((uint32_t)(((uint32_t)(x)) << GPR0_CLKOUT0SEL_CGEN_SHIFT)) & GPR0_CLKOUT0SEL_CGEN_MASK) 194 /*! @} */ 195 196 /*! @name LVFCCU0S - VFCCU Fault Status 0 */ 197 /*! @{ */ 198 199 #define GPR0_LVFCCU0S_STAT_MASK (0xFFFFFFFFU) 200 #define GPR0_LVFCCU0S_STAT_SHIFT (0U) 201 #define GPR0_LVFCCU0S_STAT_WIDTH (32U) 202 #define GPR0_LVFCCU0S_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR0_LVFCCU0S_STAT_SHIFT)) & GPR0_LVFCCU0S_STAT_MASK) 203 /*! @} */ 204 205 /*! 206 * @} 207 */ /* end of group GPR0_Register_Masks */ 208 209 /*! 210 * @} 211 */ /* end of group GPR0_Peripheral_Access_Layer */ 212 213 #endif /* #if !defined(S32Z2_GPR0_H_) */ 214
