1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2021-11-16 4 ** Build: b221019 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2021-11-16) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MIMX9352_ca55_FEATURES_H_ 26 #define _MIMX9352_ca55_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief AXBS availability on the SoC. */ 31 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 32 /* @brief DDR availability on the SoC. */ 33 #define FSL_FEATURE_SOC_DDR_COUNT (1) 34 /* @brief DMA4 availability on the SoC. */ 35 #define FSL_FEATURE_SOC_DMA4_COUNT (1) 36 /* @brief EDMA availability on the SoC. */ 37 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 38 /* @brief ENET availability on the SoC. */ 39 #define FSL_FEATURE_SOC_ENET_COUNT (1) 40 /* @brief ENET_QOS availability on the SoC. */ 41 #define FSL_FEATURE_SOC_ENET_QOS_COUNT (1) 42 /* @brief FLEXCAN availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) 44 /* @brief FLEXIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_FLEXIO_COUNT (2) 46 /* @brief FLEXSPI availability on the SoC. */ 47 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 48 /* @brief GPC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_GPC_COUNT (4) 50 /* @brief I3C availability on the SoC. */ 51 #define FSL_FEATURE_SOC_I3C_COUNT (2) 52 /* @brief I2S availability on the SoC. */ 53 #define FSL_FEATURE_SOC_I2S_COUNT (3) 54 /* @brief ISI availability on the SoC. */ 55 #define FSL_FEATURE_SOC_ISI_COUNT (1) 56 /* @brief LCDIF availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LCDIF_COUNT (1) 58 /* @brief LPI2C availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPI2C_COUNT (8) 60 /* @brief LPIT availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPIT_COUNT (2) 62 /* @brief LPSPI availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LPSPI_COUNT (8) 64 /* @brief LPTMR availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 66 /* @brief LPUART availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LPUART_COUNT (8) 68 /* @brief MCM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MCM_COUNT (1) 70 /* @brief MIPI_DSI availability on the SoC. */ 71 #define FSL_FEATURE_SOC_MIPI_DSI_COUNT (1) 72 /* @brief NPU availability on the SoC. */ 73 #define FSL_FEATURE_SOC_NPU_COUNT (1) 74 /* @brief OCOTP availability on the SoC. */ 75 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 76 /* @brief OTFAD availability on the SoC. */ 77 #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 78 /* @brief PDM availability on the SoC. */ 79 #define FSL_FEATURE_SOC_PDM_COUNT (1) 80 /* @brief PXP availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PXP_COUNT (1) 82 /* @brief RGPIO availability on the SoC. */ 83 #define FSL_FEATURE_SOC_RGPIO_COUNT (4) 84 /* @brief ROMC availability on the SoC. */ 85 #define FSL_FEATURE_SOC_ROMC_COUNT (2) 86 /* @brief SEMA42 availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SEMA42_COUNT (2) 88 /* @brief SFA availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SFA_COUNT (1) 90 /* @brief SPDIF availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SPDIF_COUNT (1) 92 /* @brief SRC availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SRC_COUNT (13) 94 /* @brief TPM availability on the SoC. */ 95 #define FSL_FEATURE_SOC_TPM_COUNT (6) 96 /* @brief TRGMUX availability on the SoC. */ 97 #define FSL_FEATURE_SOC_TRGMUX_COUNT (1) 98 /* @brief TSTMR availability on the SoC. */ 99 #define FSL_FEATURE_SOC_TSTMR_COUNT (2) 100 /* @brief USB availability on the SoC. */ 101 #define FSL_FEATURE_SOC_USB_COUNT (2) 102 /* @brief USBNC availability on the SoC. */ 103 #define FSL_FEATURE_SOC_USBNC_COUNT (2) 104 /* @brief USDHC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_USDHC_COUNT (3) 106 /* @brief WDOG availability on the SoC. */ 107 #define FSL_FEATURE_SOC_WDOG_COUNT (5) 108 /* @brief XCACHE availability on the SoC. */ 109 #define FSL_FEATURE_SOC_XCACHE_COUNT (2) 110 111 /* FLEXCAN module features */ 112 113 /* @brief Message buffer size */ 114 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) 115 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 116 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 117 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 118 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 119 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 120 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 121 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 122 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) 123 /* @brief Instance has extended bit timing register (register CBT). */ 124 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 125 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 126 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 127 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 128 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 129 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ 130 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) 131 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ 132 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) 133 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 134 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 135 /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ 136 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) 137 /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ 138 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) 139 /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ 140 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) 141 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ 142 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) 143 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ 144 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) 145 /* @brief Has memory error control (register MECR). */ 146 #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) 147 /* @brief Init memory base 1 */ 148 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) 149 /* @brief Init memory size 1 */ 150 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60) 151 /* @brief Init memory base 2 */ 152 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) 153 /* @brief Init memory size 2 */ 154 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25E0) 155 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ 156 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) 157 /* @brief Has Pretended Networking mode support. */ 158 #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) 159 /* @brief Has Enhanced Rx FIFO. */ 160 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) 161 /* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ 162 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) 163 /* @brief The number of enhanced Rx FIFO filter element registers. */ 164 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) 165 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ 166 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) 167 168 /* EDMA module features */ 169 170 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 171 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (31) 172 /* @brief Total number of DMA channels on all modules. */ 173 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (31) 174 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 175 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 176 /* @brief Has DMA_Error interrupt vector. */ 177 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 178 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 179 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 180 /* @brief If channel clock controlled independently */ 181 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 182 /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ 183 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (31) 184 /* @brief Has no register bit fields MP_CSR[EBW]. */ 185 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) 186 /* @brief If dma has channel mux */ 187 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (0) 188 /* @brief If dma has common clock gate */ 189 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) 190 /* @brief If dma channel IRQ support parameter */ 191 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) 192 /* @brief If 8 bytes transfer supported. */ 193 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 194 /* @brief If 16 bytes transfer supported. */ 195 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 196 /* @brief If 64 bytes transfer supported. */ 197 #define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) 198 /* @brief Has no register bit fields CH_SBR[ATTR]. */ 199 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) 200 201 /* DMA_TCD module features */ 202 203 /* @brief Has no supervisor access bit (CR). */ 204 #define FSL_FEATURE_DMA_TCD_HAS_NO_CR_SUP (1) 205 /* @brief Has no oscillator enable bit (CR). */ 206 #define FSL_FEATURE_DMA_TCD_HAS_NO_CR_OSCE (1) 207 208 /* ENET module features */ 209 210 /* @brief Support Interrupt Coalesce */ 211 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) 212 /* @brief Queue Size. */ 213 #define FSL_FEATURE_ENET_QUEUE (3) 214 /* @brief Has AVB Support. */ 215 #define FSL_FEATURE_ENET_HAS_AVB (1) 216 /* @brief Has Timer Pulse Width control. */ 217 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) 218 /* @brief Has Extend MDIO Support. */ 219 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 220 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 221 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) 222 /* @brief Support Interrupt Coalesce for each instance */ 223 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) 224 /* @brief Queue Size for each instance. */ 225 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) 226 /* @brief Has AVB Support for each instance. */ 227 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) 228 /* @brief Has Timer Pulse Width control for each instance. */ 229 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) 230 /* @brief Has Extend MDIO Support for each instance. */ 231 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 232 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 233 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) 234 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 235 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 236 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 237 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) 238 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 239 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) 240 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 241 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) 242 /* @brief ENET Has Extra Clock Gate.(RW610). */ 243 #define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) 244 245 /* ENET_QOS module features */ 246 247 /* No feature definitions */ 248 249 /* FLEXSPI module features */ 250 251 /* @brief FlexSPI AHB buffer count */ 252 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) 253 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 254 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) 255 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 256 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) 257 258 /* RGPIO module features */ 259 260 /* @brief Has GPIO attribute checker register (GACR). */ 261 #define FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER (0) 262 /* @brief There is ICR registers */ 263 #define FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG (1) 264 /* @brief There is PIDR register */ 265 #define FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE (1) 266 267 /* I3C module features */ 268 269 /* @brief Has TERM bitfile in MERRWARN register. */ 270 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 271 /* @brief SOC has no reset driver. */ 272 #define FSL_FEATURE_I3C_HAS_NO_RESET (1) 273 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 274 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 275 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 276 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) 277 /* @brief Register SCONFIG has HDROK bitfield. */ 278 #define FSL_FEATURE_I3C_HAS_HDROK (1) 279 280 /* CACHE module features */ 281 282 /* @brief L1 ICACHE line size in byte. */ 283 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (64) 284 /* @brief L1 DCACHE line size in byte. */ 285 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) 286 /* @brief Has NONCACHEABLE section. */ 287 #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) 288 289 /* LPI2C module features */ 290 291 /* @brief Has separate DMA RX and TX requests. */ 292 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 293 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 294 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) 295 296 /* LPIT module features */ 297 298 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 299 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 300 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 301 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 302 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 303 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 304 305 /* LPSPI module features */ 306 307 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 308 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) 309 /* @brief Has separate DMA RX and TX requests. */ 310 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 311 /* @brief Has CCR1 (related to existence of registers CCR1). */ 312 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) 313 314 /* LPTMR module features */ 315 316 /* @brief Has shared interrupt handler with another LPTMR module. */ 317 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 318 /* @brief Whether LPTMR counter is 32 bits width. */ 319 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) 320 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 321 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 322 /* @brief Do not has prescaler clock source 1. */ 323 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) 324 /* @brief Do not has prescaler clock source 3. */ 325 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) 326 327 /* LPUART module features */ 328 329 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 330 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 331 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 332 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 333 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 334 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 335 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 336 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 337 /* @brief Has 32-bit register MODIR */ 338 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 339 /* @brief Hardware flow control (RTS, CTS) is supported. */ 340 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 341 /* @brief Infrared (modulation) is supported. */ 342 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 343 /* @brief 2 bits long stop bit is available. */ 344 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 345 /* @brief If 10-bit mode is supported. */ 346 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 347 /* @brief If 7-bit mode is supported. */ 348 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 349 /* @brief Baud rate fine adjustment is available. */ 350 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 351 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 352 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 353 /* @brief Baud rate oversampling is available. */ 354 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 355 /* @brief Baud rate oversampling is available. */ 356 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 357 /* @brief Peripheral type. */ 358 #define FSL_FEATURE_LPUART_IS_SCI (1) 359 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 360 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) 361 /* @brief Supports two match addresses to filter incoming frames. */ 362 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 363 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 364 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 365 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 366 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 367 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 368 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 369 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 370 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 371 /* @brief Has improved smart card (ISO7816 protocol) support. */ 372 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 373 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 374 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 375 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 376 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 377 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 378 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 379 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 380 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 381 /* @brief Has separate DMA RX and TX requests. */ 382 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 383 /* @brief Has separate RX and TX interrupts. */ 384 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 385 /* @brief Has LPAURT_PARAM. */ 386 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 387 /* @brief Has LPUART_VERID. */ 388 #define FSL_FEATURE_LPUART_HAS_VERID (1) 389 /* @brief Has LPUART_GLOBAL. */ 390 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 391 /* @brief Has LPUART_PINCFG. */ 392 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 393 394 /* MEMORY module features */ 395 396 /* @brief Memory map doesn't have offset between subsystems. */ 397 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) 398 399 /* PDM module features */ 400 401 /* @brief PDM FIFO offset */ 402 #define FSL_FEATURE_PDM_FIFO_OFFSET (4) 403 /* @brief PDM Channel Number */ 404 #define FSL_FEATURE_PDM_CHANNEL_NUM (8) 405 /* @brief PDM FIFO WIDTH Size */ 406 #define FSL_FEATURE_PDM_FIFO_WIDTH (4) 407 /* @brief PDM FIFO DEPTH Size */ 408 #define FSL_FEATURE_PDM_FIFO_DEPTH (8) 409 /* @brief PDM has RANGE_CTRL register */ 410 #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) 411 /* @brief PDM Has Low Frequency */ 412 #define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1) 413 /* @brief CLKDIV factor in Medium, High and Low Quality modes */ 414 #define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (93) 415 /* @brief CLKDIV factor in Very Low Quality modes */ 416 #define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (43) 417 /* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ 418 #define FSL_FEATURE_PDM_HAS_NO_VADEF (0) 419 /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ 420 #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) 421 422 /* SAI module features */ 423 424 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 425 #define FSL_FEATURE_SAI_HAS_FIFO (1) 426 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 427 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ 428 (((x) == SAI1) ? (32) : \ 429 (((x) == SAI2) ? (128) : \ 430 (((x) == SAI3) ? (128) : (-1)))) 431 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 432 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ 433 (((x) == SAI1) ? (2) : \ 434 (((x) == SAI2) ? (4) : \ 435 (((x) == SAI3) ? (1) : (-1)))) 436 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 437 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 438 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 439 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 440 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 441 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 442 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 443 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 444 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 445 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 446 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 447 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 448 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 449 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 450 /* @brief Has register of MCR. */ 451 #define FSL_FEATURE_SAI_HAS_MCR (1) 452 /* @brief Has bit field MICS of the MCR register. */ 453 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 454 /* @brief Has register of MDR */ 455 #define FSL_FEATURE_SAI_HAS_MDR (0) 456 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 457 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) 458 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 459 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) 460 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 461 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 462 /* @brief Used to retrieve the physical base address of a transmit FIFO. 463 * The index of the transmit FIFO is specified through the fifo_index argument. 464 * The sai_base argument needs to be the physical base address of the SAI. 465 */ 466 #define FSL_FEATURE_SAI_TX_FIFO_BASEn(sai_base, fifo_index)\ 467 (((sai_base) == SAI1) ? ((uintptr_t)SAI1 + 0x20 + (fifo_index) * 0x4) :\ 468 (((sai_base) == SAI2) ? ((uintptr_t)SAI2 + 0x20 + (fifo_index) * 0x4) :\ 469 (((sai_base) == SAI3) ? ((uintptr_t)SAI3 + 0x20 + (fifo_index) * 0x4) : (0)))) 470 /* @brief Used to retrieve the physical base address of a receive FIFO. 471 * The index of the receive FIFO is specified through the fifo_index argument. 472 * The sai_base argument needs to be the physical base address of the SAI. 473 */ 474 #define FSL_FEATURE_SAI_RX_FIFO_BASEn(sai_base, fifo_index)\ 475 (((sai_base) == SAI1) ? ((uintptr_t)SAI1 + 0xa0 + (fifo_index) * 0x4) :\ 476 (((sai_base) == SAI2) ? ((uintptr_t)SAI2 + 0xa0 + (fifo_index) * 0x4) :\ 477 (((sai_base) == SAI3) ? ((uintptr_t)SAI3 + 0xa0 + (fifo_index) * 0x4) : (0)))) 478 /* @brief Used to retrieve the DMA MUX value for a SAI's transmitter. 479 * The sai_base argument needs to be the physical base address of the SAI. 480 */ 481 #define FSL_FEATURE_SAI_TX_DMA_MUXn(sai_base)\ 482 (((sai_base) == SAI1) ? (21) : \ 483 (((sai_base) == SAI2) ? (58) : \ 484 (((sai_base) == SAI3) ? (60) : (0)))) 485 /* @brief Used to retrieve the DMA MUX value for a SAI's receiver. 486 * The sai_base argument needs to be the physical base address of the SAI. 487 */ 488 #define FSL_FEATURE_SAI_RX_DMA_MUXn(sai_base)\ 489 (((sai_base) == SAI1) ? (22) : \ 490 (((sai_base) == SAI2) ? (59) : \ 491 (((sai_base) == SAI3) ? (61) : (0)))) 492 493 /* SEMA42 module features */ 494 495 /* @brief Gate counts */ 496 #define FSL_FEATURE_SEMA42_GATE_COUNT (64) 497 498 /* TPM module features */ 499 500 /* @brief Number of channels. */ 501 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (4) 502 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 503 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 504 /* @brief Has TPM_PARAM. */ 505 #define FSL_FEATURE_TPM_HAS_PARAM (1) 506 /* @brief Has TPM_VERID. */ 507 #define FSL_FEATURE_TPM_HAS_VERID (1) 508 /* @brief Has TPM_GLOBAL. */ 509 #define FSL_FEATURE_TPM_HAS_GLOBAL (1) 510 /* @brief Has TPM_TRIG. */ 511 #define FSL_FEATURE_TPM_HAS_TRIG (1) 512 /* @brief Whether TRIG register has effect. */ 513 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) 514 /* @brief Has counter pause on trigger. */ 515 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 516 /* @brief Has external trigger selection. */ 517 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 518 /* @brief Has TPM_COMBINE register. */ 519 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 520 /* @brief Whether COMBINE register has effect. */ 521 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 522 /* @brief Has TPM_POL. */ 523 #define FSL_FEATURE_TPM_HAS_POL (1) 524 /* @brief Whether POL register has effect. */ 525 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (0) 526 /* @brief Has TPM_FILTER register. */ 527 #define FSL_FEATURE_TPM_HAS_FILTER (1) 528 /* @brief Whether FILTER register has effect. */ 529 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 530 /* @brief Has TPM_QDCTRL register. */ 531 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 532 /* @brief Whether QDCTRL register has effect. */ 533 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 534 /* @brief Has pause level select. */ 535 #define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1) 536 /* @brief Whether 32 bits counter has effect. */ 537 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (1) 538 539 /* TRDC module features */ 540 541 /* @brief Process master count. */ 542 #define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) 543 /* @brief TRDC instance has PID configuration or not. */ 544 #define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) \ 545 (((x) == TRDC1) ? (1) : \ 546 (((x) == TRDC2) ? (0) : (-1))) 547 /* @brief TRDC domain number (reset value of HWCFG0[NDID]). */ 548 #define FSL_FEATURE_TRDC_DOMAIN_COUNT (16) 549 550 /* TSTMR module features */ 551 552 /* @brief TSTMR clock frequency is 1MHZ. */ 553 #define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1) 554 555 /* USDHC module features */ 556 557 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 558 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) 559 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 560 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 561 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 562 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 563 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 564 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 565 /* @brief USDHC has reset control */ 566 #define FSL_FEATURE_USDHC_HAS_RESET (0) 567 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 568 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) 569 /* @brief If USDHC instance support 8 bit width */ 570 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 571 /* @brief If USDHC instance support HS400 mode */ 572 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) 573 /* @brief If USDHC instance support 1v8 signal */ 574 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 575 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 576 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) 577 578 /* WDOG module features */ 579 580 /* @brief Watchdog is available. */ 581 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 582 /* @brief WDOG_CNT can be 32-bit written. */ 583 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 584 585 #endif /* _MIMX9352_ca55_FEATURES_H_ */ 586
