1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2023 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_FLEXRAY.h
10  * @version 2.1
11  * @date 2023-07-20
12  * @brief Peripheral Access Layer for S32Z2_FLEXRAY
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_FLEXRAY_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_FLEXRAY_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- FLEXRAY Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup FLEXRAY_Peripheral_Access_Layer FLEXRAY Peripheral Access Layer
68  * @{
69  */
70 
71 /** FLEXRAY - Size of Registers Arrays */
72 #define FLEXRAY_NMVR_COUNT                        6u
73 #define FLEXRAY_SSR_COUNT                         8u
74 #define FLEXRAY_SSCR_COUNT                        4u
75 #define FLEXRAY_MB_COUNT                          256u
76 #define FLEXRAY_MBDOR_COUNT                       260u
77 #define FLEXRAY_LEETR_COUNT                       6u
78 
79 /** FLEXRAY - Register Layout Typedef */
80 typedef struct {
81   __I  uint16_t MVR;                               /**< Module Version, offset: 0x0 */
82   __IO uint16_t MCR;                               /**< Module Configuration, offset: 0x2 */
83   __IO uint16_t SYMBADHR;                          /**< System Memory Base Address High, offset: 0x4 */
84   __IO uint16_t SYMBADLR;                          /**< System Memory Base Address Low, offset: 0x6 */
85   __IO uint16_t STBSCR;                            /**< Strobe Signal Control, offset: 0x8 */
86   uint8_t RESERVED_0[2];
87   __IO uint16_t MBDSR;                             /**< MB Data Size, offset: 0xC */
88   __IO uint16_t MBSSUTR;                           /**< MB Segment Size and Utilization, offset: 0xE */
89   __IO uint16_t PEDRAR;                            /**< PE DRAM Access, offset: 0x10 */
90   __IO uint16_t PEDRDR;                            /**< PE DRAM Data, offset: 0x12 */
91   __IO uint16_t POCR;                              /**< Protocol Operation Control, offset: 0x14 */
92   __IO uint16_t GIFER;                             /**< Global Interrupt Flag And Enable, offset: 0x16 */
93   __IO uint16_t PIFR0;                             /**< Protocol Interrupt Flag 0, offset: 0x18 */
94   __IO uint16_t PIFR1;                             /**< Protocol Interrupt Flag 1, offset: 0x1A */
95   __IO uint16_t PIER0;                             /**< Protocol Interrupt Enable 0, offset: 0x1C */
96   __IO uint16_t PIER1;                             /**< Protocol Interrupt Enable 1, offset: 0x1E */
97   __IO uint16_t CHIERFR;                           /**< CHI Error Flag, offset: 0x20 */
98   __I  uint16_t MBIVEC;                            /**< MB Interrupt Vector, offset: 0x22 */
99   __I  uint16_t CASERCR;                           /**< Channel A Status Error Counter Register, offset: 0x24 */
100   __I  uint16_t CBSERCR;                           /**< Channel B Status Error Counter, offset: 0x26 */
101   __I  uint16_t PSR0;                              /**< Protocol Status 0, offset: 0x28 */
102   __IO uint16_t PSR1;                              /**< Protocol Status 1, offset: 0x2A */
103   __I  uint16_t PSR2;                              /**< Protocol Status 2, offset: 0x2C */
104   __IO uint16_t PSR3;                              /**< Protocol Status 3, offset: 0x2E */
105   __I  uint16_t MTCTR;                             /**< MT Counter, offset: 0x30 */
106   __I  uint16_t CYCTR;                             /**< Cycle Counter, offset: 0x32 */
107   __I  uint16_t SLTCTAR;                           /**< Slot Counter Channel A, offset: 0x34 */
108   __I  uint16_t SLTCTBR;                           /**< Slot Counter Channel B, offset: 0x36 */
109   __I  uint16_t RTCORVR;                           /**< Rate Correction Value, offset: 0x38 */
110   __I  uint16_t OFCORVR;                           /**< Offset Correction Value, offset: 0x3A */
111   __I  uint16_t CIFR;                              /**< Combined Interrupt Flag, offset: 0x3C */
112   __IO uint16_t SYMATOR;                           /**< System Memory Access Timeout, offset: 0x3E */
113   __I  uint16_t SFCNTR;                            /**< Sync Frame Counter, offset: 0x40 */
114   __IO uint16_t SFTOR;                             /**< Sync Frame Table Offset, offset: 0x42 */
115   __IO uint16_t SFTCCSR;                           /**< Sync Frame Table Configuration Control Status, offset: 0x44 */
116   __IO uint16_t SFIDRFR;                           /**< Sync Frame ID Rejection Filter, offset: 0x46 */
117   __IO uint16_t SFIDAFVR;                          /**< Sync Frame ID Acceptance Filter Value, offset: 0x48 */
118   __IO uint16_t SFIDAFMR;                          /**< Sync Frame ID Acceptance Filter Mask, offset: 0x4A */
119   __I  uint16_t NMVR[FLEXRAY_NMVR_COUNT];          /**< NMV 0..NMV 5, array offset: 0x4C, array step: 0x2 */
120   __IO uint16_t NMVLR;                             /**< Network Management Vector Length Register, offset: 0x58 */
121   __IO uint16_t TICCR;                             /**< Timer Configuration And Control, offset: 0x5A */
122   __IO uint16_t TI1CYSR;                           /**< Timer 1 Cycle Set, offset: 0x5C */
123   __IO uint16_t TI1MTOR;                           /**< Timer 1 MT Offset, offset: 0x5E */
124   union {                                          /* offset: 0x60 */
125     __IO uint16_t ABS;                               /**< Timer 2 Configuration 0 (Absolute Timer Configuration), offset: 0x60 */
126     __IO uint16_t REL;                               /**< Timer 2 Configuration 0 (Relative Timer Configuration), offset: 0x60 */
127   } TI2CR0;
128   union {                                          /* offset: 0x62 */
129     __IO uint16_t ABS;                               /**< Timer 2 Configuration 1 (Absolute Timer Configuration), offset: 0x62 */
130     __IO uint16_t REL;                               /**< Timer 2 Configuration 1 (Relative Timer Configuration), offset: 0x62 */
131   } TI2CR1;
132   __IO uint16_t SSSR;                              /**< Slot Status Selection, offset: 0x64 */
133   __IO uint16_t SSCCR;                             /**< Slot Status Counter Condition, offset: 0x66 */
134   __I  uint16_t SSR[FLEXRAY_SSR_COUNT];            /**< Slot Status, array offset: 0x68, array step: 0x2 */
135   __I  uint16_t SSCR[FLEXRAY_SSCR_COUNT];          /**< Slot Status Counter, array offset: 0x78, array step: 0x2 */
136   __IO uint16_t MTSACFR;                           /**< MTS A Configuration, offset: 0x80 */
137   __IO uint16_t MTSBCFR;                           /**< MTS B Configuration, offset: 0x82 */
138   __IO uint16_t RSBIR;                             /**< Receive Shadow Buffer Index, offset: 0x84 */
139   __IO uint16_t RFWMSR;                            /**< Receive FIFO Watermark And Selection, offset: 0x86 */
140   __IO uint16_t RFSIR;                             /**< Receive FIFO Start Index, offset: 0x88 */
141   __IO uint16_t RFDSR;                             /**< Receive FIFO Depth And Size, offset: 0x8A */
142   __I  uint16_t RFARIR;                            /**< Receive FIFO A Read Index, offset: 0x8C */
143   __I  uint16_t RFBRIR;                            /**< Receive FIFO B Read Index, offset: 0x8E */
144   __IO uint16_t RFMIDAFVR;                         /**< Receive FIFO Message ID Acceptance Filter Value, offset: 0x90 */
145   __IO uint16_t RFMIDAFMR;                         /**< Receive FIFO Message ID Acceptance Filter Mask, offset: 0x92 */
146   __IO uint16_t RFFIDRFVR;                         /**< Receive FIFO Frame ID Rejection Filter Value, offset: 0x94 */
147   __IO uint16_t RFFIDRFMR;                         /**< Receive FIFO Frame ID Rejection Filter Mask, offset: 0x96 */
148   __IO uint16_t RFRFCFR;                           /**< Receive FIFO Range Filter Configuration, offset: 0x98 */
149   __IO uint16_t RFRFCTR;                           /**< Receive FIFO Range Filter Control, offset: 0x9A */
150   __I  uint16_t LDTXSLAR;                          /**< Last Dynamic Transmit Slot Channel A, offset: 0x9C */
151   __I  uint16_t LDTXSLBR;                          /**< Last Dynamic Transmit Slot Channel B, offset: 0x9E */
152   __IO uint16_t PCR0;                              /**< Protocol Configuration 0, offset: 0xA0 */
153   __IO uint16_t PCR1;                              /**< Protocol Configuration 1, offset: 0xA2 */
154   __IO uint16_t PCR2;                              /**< Protocol Configuration 2, offset: 0xA4 */
155   __IO uint16_t PCR3;                              /**< Protocol Configuration 3, offset: 0xA6 */
156   __IO uint16_t PCR4;                              /**< Protocol Configuration 4, offset: 0xA8 */
157   __IO uint16_t PCR5;                              /**< Protocol Configuration 5, offset: 0xAA */
158   __IO uint16_t PCR6;                              /**< Protocol Configuration 6, offset: 0xAC */
159   __IO uint16_t PCR7;                              /**< Protocol Configuration 7, offset: 0xAE */
160   __IO uint16_t PCR8;                              /**< Protocol Configuration 8, offset: 0xB0 */
161   __IO uint16_t PCR9;                              /**< Protocol Configuration 9, offset: 0xB2 */
162   __IO uint16_t PCR10;                             /**< Protocol Configuration 10, offset: 0xB4 */
163   __IO uint16_t PCR11;                             /**< Protocol Configuration 11, offset: 0xB6 */
164   __IO uint16_t PCR12;                             /**< Protocol Configuration 12, offset: 0xB8 */
165   __IO uint16_t PCR13;                             /**< Protocol Configuration 13, offset: 0xBA */
166   __IO uint16_t PCR14;                             /**< Protocol Configuration 14, offset: 0xBC */
167   __IO uint16_t PCR15;                             /**< Protocol Configuration 15, offset: 0xBE */
168   __IO uint16_t PCR16;                             /**< Protocol Configuration 16, offset: 0xC0 */
169   __IO uint16_t PCR17;                             /**< Protocol Configuration 17, offset: 0xC2 */
170   __IO uint16_t PCR18;                             /**< Protocol Configuration 18, offset: 0xC4 */
171   __IO uint16_t PCR19;                             /**< Protocol Configuration 19, offset: 0xC6 */
172   __IO uint16_t PCR20;                             /**< Protocol Configuration 20, offset: 0xC8 */
173   __IO uint16_t PCR21;                             /**< Protocol Configuration 21, offset: 0xCA */
174   __IO uint16_t PCR22;                             /**< Protocol Configuration 22, offset: 0xCC */
175   __IO uint16_t PCR23;                             /**< Protocol Configuration 23, offset: 0xCE */
176   __IO uint16_t PCR24;                             /**< Protocol Configuration 24, offset: 0xD0 */
177   __IO uint16_t PCR25;                             /**< Protocol Configuration 25, offset: 0xD2 */
178   __IO uint16_t PCR26;                             /**< Protocol Configuration 26, offset: 0xD4 */
179   __IO uint16_t PCR27;                             /**< Protocol Configuration 27, offset: 0xD6 */
180   __IO uint16_t PCR28;                             /**< Protocol Configuration 28, offset: 0xD8 */
181   __IO uint16_t PCR29;                             /**< Protocol Configuration 29, offset: 0xDA */
182   __IO uint16_t PCR30;                             /**< Protocol Configuration 30, offset: 0xDC */
183   __IO uint16_t STPWHR;                            /**< Stopwatch Count High, offset: 0xDE */
184   __IO uint16_t STPWLR;                            /**< Stopwatch Count Low, offset: 0xE0 */
185   __IO uint16_t PEOER;                             /**< Protocol Event Output Enable And Stopwatch Control, offset: 0xE2 */
186   uint8_t RESERVED_1[2];
187   __IO uint16_t RFSDOR;                            /**< Receive FIFO Start Data Offset, offset: 0xE6 */
188   __IO uint16_t RFSYMBADHR;                        /**< Receive FIFO System Memory Base Address High, offset: 0xE8 */
189   __IO uint16_t RFSYMBADLR;                        /**< Receive FIFO System Memory Base Address Low, offset: 0xEA */
190   __IO uint16_t RFPTR;                             /**< Receive FIFO Periodic Timer, offset: 0xEC */
191   __IO uint16_t RFFLPCR;                           /**< Receive FIFO Fill Level and Pop Count, offset: 0xEE */
192   __IO uint16_t EEIFER;                            /**< ECC Error Interrupt Flag And Enable, offset: 0xF0 */
193   __IO uint16_t EERICR;                            /**< ECC Error Report And Injection Control, offset: 0xF2 */
194   __I  uint16_t EERAR;                             /**< ECC Error Report Address, offset: 0xF4 */
195   __I  uint16_t EERDR;                             /**< ECC Error Report Data, offset: 0xF6 */
196   __I  uint16_t EERCR;                             /**< ECC Error Report Code, offset: 0xF8 */
197   __IO uint16_t EEIAR;                             /**< ECC Error Injection Address, offset: 0xFA */
198   __IO uint16_t EEIDR;                             /**< ECC Error Injection Data, offset: 0xFC */
199   __IO uint16_t EEICR;                             /**< ECC Error Injection Code, offset: 0xFE */
200   uint8_t RESERVED_2[1792];
201   struct {                                         /* offset: 0x800, array step: 0x8 */
202     __IO uint16_t CCSR;                              /**< MB Configuration Control Status, array offset: 0x800, array step: 0x8 */
203     __IO uint16_t CCFR;                              /**< MB Cycle Counter Filter, array offset: 0x802, array step: 0x8 */
204     __IO uint16_t FIDR;                              /**< MB FID, array offset: 0x804, array step: 0x8 */
205     __IO uint16_t IDXR;                              /**< MB Index, array offset: 0x806, array step: 0x8 */
206   } MB[FLEXRAY_MB_COUNT];
207   __IO uint16_t MBDOR[FLEXRAY_MBDOR_COUNT];        /**< MB Data Field Offset, array offset: 0x1000, array step: 0x2 */
208   uint8_t RESERVED_3[8];
209   __IO uint16_t LEETR[FLEXRAY_LEETR_COUNT];        /**< LRAM ECC Error Test Register, array offset: 0x1210, array step: 0x2 */
210 } FLEXRAY_Type, *FLEXRAY_MemMapPtr;
211 
212 /** Number of instances of the FLEXRAY module. */
213 #define FLEXRAY_INSTANCE_COUNT                   (2u)
214 
215 /* FLEXRAY - Peripheral instance base addresses */
216 /** Peripheral FR_0 base address */
217 #define IP_FR_0_BASE                             (0x401B0000u)
218 /** Peripheral FR_0 base pointer */
219 #define IP_FR_0                                  ((FLEXRAY_Type *)IP_FR_0_BASE)
220 /** Peripheral FR_1 base address */
221 #define IP_FR_1_BASE                             (0x401C0000u)
222 /** Peripheral FR_1 base pointer */
223 #define IP_FR_1                                  ((FLEXRAY_Type *)IP_FR_1_BASE)
224 /** Array initializer of FLEXRAY peripheral base addresses */
225 #define IP_FLEXRAY_BASE_ADDRS                    { IP_FR_0_BASE, IP_FR_1_BASE }
226 /** Array initializer of FLEXRAY peripheral base pointers */
227 #define IP_FLEXRAY_BASE_PTRS                     { IP_FR_0, IP_FR_1 }
228 
229 /* ----------------------------------------------------------------------------
230    -- FLEXRAY Register Masks
231    ---------------------------------------------------------------------------- */
232 
233 /*!
234  * @addtogroup FLEXRAY_Register_Masks FLEXRAY Register Masks
235  * @{
236  */
237 
238 /*! @name MVR - Module Version */
239 /*! @{ */
240 
241 #define FLEXRAY_MVR_PEVER_MASK                   (0xFFU)
242 #define FLEXRAY_MVR_PEVER_SHIFT                  (0U)
243 #define FLEXRAY_MVR_PEVER_WIDTH                  (8U)
244 #define FLEXRAY_MVR_PEVER(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MVR_PEVER_SHIFT)) & FLEXRAY_MVR_PEVER_MASK)
245 
246 #define FLEXRAY_MVR_CHIVER_MASK                  (0xFF00U)
247 #define FLEXRAY_MVR_CHIVER_SHIFT                 (8U)
248 #define FLEXRAY_MVR_CHIVER_WIDTH                 (8U)
249 #define FLEXRAY_MVR_CHIVER(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MVR_CHIVER_SHIFT)) & FLEXRAY_MVR_CHIVER_MASK)
250 /*! @} */
251 
252 /*! @name MCR - Module Configuration */
253 /*! @{ */
254 
255 #define FLEXRAY_MCR_BITRATE_MASK                 (0xEU)
256 #define FLEXRAY_MCR_BITRATE_SHIFT                (1U)
257 #define FLEXRAY_MCR_BITRATE_WIDTH                (3U)
258 #define FLEXRAY_MCR_BITRATE(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_BITRATE_SHIFT)) & FLEXRAY_MCR_BITRATE_MASK)
259 
260 #define FLEXRAY_MCR_FAM_MASK                     (0x40U)
261 #define FLEXRAY_MCR_FAM_SHIFT                    (6U)
262 #define FLEXRAY_MCR_FAM_WIDTH                    (1U)
263 #define FLEXRAY_MCR_FAM(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_FAM_SHIFT)) & FLEXRAY_MCR_FAM_MASK)
264 
265 #define FLEXRAY_MCR_FUM_MASK                     (0x80U)
266 #define FLEXRAY_MCR_FUM_SHIFT                    (7U)
267 #define FLEXRAY_MCR_FUM_WIDTH                    (1U)
268 #define FLEXRAY_MCR_FUM(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_FUM_SHIFT)) & FLEXRAY_MCR_FUM_MASK)
269 
270 #define FLEXRAY_MCR_ECCE_MASK                    (0x200U)
271 #define FLEXRAY_MCR_ECCE_SHIFT                   (9U)
272 #define FLEXRAY_MCR_ECCE_WIDTH                   (1U)
273 #define FLEXRAY_MCR_ECCE(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_ECCE_SHIFT)) & FLEXRAY_MCR_ECCE_MASK)
274 
275 #define FLEXRAY_MCR_SFFE_MASK                    (0x400U)
276 #define FLEXRAY_MCR_SFFE_SHIFT                   (10U)
277 #define FLEXRAY_MCR_SFFE_WIDTH                   (1U)
278 #define FLEXRAY_MCR_SFFE(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_SFFE_SHIFT)) & FLEXRAY_MCR_SFFE_MASK)
279 
280 #define FLEXRAY_MCR_CHA_MASK                     (0x800U)
281 #define FLEXRAY_MCR_CHA_SHIFT                    (11U)
282 #define FLEXRAY_MCR_CHA_WIDTH                    (1U)
283 #define FLEXRAY_MCR_CHA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_CHA_SHIFT)) & FLEXRAY_MCR_CHA_MASK)
284 
285 #define FLEXRAY_MCR_CHB_MASK                     (0x1000U)
286 #define FLEXRAY_MCR_CHB_SHIFT                    (12U)
287 #define FLEXRAY_MCR_CHB_WIDTH                    (1U)
288 #define FLEXRAY_MCR_CHB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_CHB_SHIFT)) & FLEXRAY_MCR_CHB_MASK)
289 
290 #define FLEXRAY_MCR_SCM_MASK                     (0x2000U)
291 #define FLEXRAY_MCR_SCM_SHIFT                    (13U)
292 #define FLEXRAY_MCR_SCM_WIDTH                    (1U)
293 #define FLEXRAY_MCR_SCM(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_SCM_SHIFT)) & FLEXRAY_MCR_SCM_MASK)
294 
295 #define FLEXRAY_MCR_SBFF_MASK                    (0x4000U)
296 #define FLEXRAY_MCR_SBFF_SHIFT                   (14U)
297 #define FLEXRAY_MCR_SBFF_WIDTH                   (1U)
298 #define FLEXRAY_MCR_SBFF(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_SBFF_SHIFT)) & FLEXRAY_MCR_SBFF_MASK)
299 
300 #define FLEXRAY_MCR_MEN_MASK                     (0x8000U)
301 #define FLEXRAY_MCR_MEN_SHIFT                    (15U)
302 #define FLEXRAY_MCR_MEN_WIDTH                    (1U)
303 #define FLEXRAY_MCR_MEN(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MCR_MEN_SHIFT)) & FLEXRAY_MCR_MEN_MASK)
304 /*! @} */
305 
306 /*! @name SYMBADHR - System Memory Base Address High */
307 /*! @{ */
308 
309 #define FLEXRAY_SYMBADHR_SMBA_MASK               (0xFFFFU)
310 #define FLEXRAY_SYMBADHR_SMBA_SHIFT              (0U)
311 #define FLEXRAY_SYMBADHR_SMBA_WIDTH              (16U)
312 #define FLEXRAY_SYMBADHR_SMBA(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SYMBADHR_SMBA_SHIFT)) & FLEXRAY_SYMBADHR_SMBA_MASK)
313 /*! @} */
314 
315 /*! @name SYMBADLR - System Memory Base Address Low */
316 /*! @{ */
317 
318 #define FLEXRAY_SYMBADLR_SMBA_MASK               (0xFFF0U)
319 #define FLEXRAY_SYMBADLR_SMBA_SHIFT              (4U)
320 #define FLEXRAY_SYMBADLR_SMBA_WIDTH              (12U)
321 #define FLEXRAY_SYMBADLR_SMBA(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SYMBADLR_SMBA_SHIFT)) & FLEXRAY_SYMBADLR_SMBA_MASK)
322 /*! @} */
323 
324 /*! @name STBSCR - Strobe Signal Control */
325 /*! @{ */
326 
327 #define FLEXRAY_STBSCR_STBPSEL_MASK              (0x3U)
328 #define FLEXRAY_STBSCR_STBPSEL_SHIFT             (0U)
329 #define FLEXRAY_STBSCR_STBPSEL_WIDTH             (2U)
330 #define FLEXRAY_STBSCR_STBPSEL(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STBSCR_STBPSEL_SHIFT)) & FLEXRAY_STBSCR_STBPSEL_MASK)
331 
332 #define FLEXRAY_STBSCR_ENB_MASK                  (0x10U)
333 #define FLEXRAY_STBSCR_ENB_SHIFT                 (4U)
334 #define FLEXRAY_STBSCR_ENB_WIDTH                 (1U)
335 #define FLEXRAY_STBSCR_ENB(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STBSCR_ENB_SHIFT)) & FLEXRAY_STBSCR_ENB_MASK)
336 
337 #define FLEXRAY_STBSCR_SEL_MASK                  (0xF00U)
338 #define FLEXRAY_STBSCR_SEL_SHIFT                 (8U)
339 #define FLEXRAY_STBSCR_SEL_WIDTH                 (4U)
340 #define FLEXRAY_STBSCR_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STBSCR_SEL_SHIFT)) & FLEXRAY_STBSCR_SEL_MASK)
341 
342 #define FLEXRAY_STBSCR_WMD_MASK                  (0x8000U)
343 #define FLEXRAY_STBSCR_WMD_SHIFT                 (15U)
344 #define FLEXRAY_STBSCR_WMD_WIDTH                 (1U)
345 #define FLEXRAY_STBSCR_WMD(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STBSCR_WMD_SHIFT)) & FLEXRAY_STBSCR_WMD_MASK)
346 /*! @} */
347 
348 /*! @name MBDSR - MB Data Size */
349 /*! @{ */
350 
351 #define FLEXRAY_MBDSR_MBSEG1DS_MASK              (0x7FU)
352 #define FLEXRAY_MBDSR_MBSEG1DS_SHIFT             (0U)
353 #define FLEXRAY_MBDSR_MBSEG1DS_WIDTH             (7U)
354 #define FLEXRAY_MBDSR_MBSEG1DS(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBDSR_MBSEG1DS_SHIFT)) & FLEXRAY_MBDSR_MBSEG1DS_MASK)
355 
356 #define FLEXRAY_MBDSR_MBSEG2DS_MASK              (0x7F00U)
357 #define FLEXRAY_MBDSR_MBSEG2DS_SHIFT             (8U)
358 #define FLEXRAY_MBDSR_MBSEG2DS_WIDTH             (7U)
359 #define FLEXRAY_MBDSR_MBSEG2DS(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBDSR_MBSEG2DS_SHIFT)) & FLEXRAY_MBDSR_MBSEG2DS_MASK)
360 /*! @} */
361 
362 /*! @name MBSSUTR - MB Segment Size and Utilization */
363 /*! @{ */
364 
365 #define FLEXRAY_MBSSUTR_LAST_MB_UTIL_MASK        (0xFFU)
366 #define FLEXRAY_MBSSUTR_LAST_MB_UTIL_SHIFT       (0U)
367 #define FLEXRAY_MBSSUTR_LAST_MB_UTIL_WIDTH       (8U)
368 #define FLEXRAY_MBSSUTR_LAST_MB_UTIL(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBSSUTR_LAST_MB_UTIL_SHIFT)) & FLEXRAY_MBSSUTR_LAST_MB_UTIL_MASK)
369 
370 #define FLEXRAY_MBSSUTR_LAST_MB_SEG1_MASK        (0xFF00U)
371 #define FLEXRAY_MBSSUTR_LAST_MB_SEG1_SHIFT       (8U)
372 #define FLEXRAY_MBSSUTR_LAST_MB_SEG1_WIDTH       (8U)
373 #define FLEXRAY_MBSSUTR_LAST_MB_SEG1(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBSSUTR_LAST_MB_SEG1_SHIFT)) & FLEXRAY_MBSSUTR_LAST_MB_SEG1_MASK)
374 /*! @} */
375 
376 /*! @name PEDRAR - PE DRAM Access */
377 /*! @{ */
378 
379 #define FLEXRAY_PEDRAR_DAD_MASK                  (0x1U)
380 #define FLEXRAY_PEDRAR_DAD_SHIFT                 (0U)
381 #define FLEXRAY_PEDRAR_DAD_WIDTH                 (1U)
382 #define FLEXRAY_PEDRAR_DAD(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PEDRAR_DAD_SHIFT)) & FLEXRAY_PEDRAR_DAD_MASK)
383 
384 #define FLEXRAY_PEDRAR_ADDR_MASK                 (0xFFEU)
385 #define FLEXRAY_PEDRAR_ADDR_SHIFT                (1U)
386 #define FLEXRAY_PEDRAR_ADDR_WIDTH                (11U)
387 #define FLEXRAY_PEDRAR_ADDR(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PEDRAR_ADDR_SHIFT)) & FLEXRAY_PEDRAR_ADDR_MASK)
388 
389 #define FLEXRAY_PEDRAR_INST_MASK                 (0xF000U)
390 #define FLEXRAY_PEDRAR_INST_SHIFT                (12U)
391 #define FLEXRAY_PEDRAR_INST_WIDTH                (4U)
392 #define FLEXRAY_PEDRAR_INST(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PEDRAR_INST_SHIFT)) & FLEXRAY_PEDRAR_INST_MASK)
393 /*! @} */
394 
395 /*! @name PEDRDR - PE DRAM Data */
396 /*! @{ */
397 
398 #define FLEXRAY_PEDRDR_DATA_MASK                 (0xFFFFU)
399 #define FLEXRAY_PEDRDR_DATA_SHIFT                (0U)
400 #define FLEXRAY_PEDRDR_DATA_WIDTH                (16U)
401 #define FLEXRAY_PEDRDR_DATA(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PEDRDR_DATA_SHIFT)) & FLEXRAY_PEDRDR_DATA_MASK)
402 /*! @} */
403 
404 /*! @name POCR - Protocol Operation Control */
405 /*! @{ */
406 
407 #define FLEXRAY_POCR_POCCMD_MASK                 (0xFU)
408 #define FLEXRAY_POCR_POCCMD_SHIFT                (0U)
409 #define FLEXRAY_POCR_POCCMD_WIDTH                (4U)
410 #define FLEXRAY_POCR_POCCMD(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_POCR_POCCMD_SHIFT)) & FLEXRAY_POCR_POCCMD_MASK)
411 
412 #define FLEXRAY_POCR_BSY_WMC_MASK                (0x80U)
413 #define FLEXRAY_POCR_BSY_WMC_SHIFT               (7U)
414 #define FLEXRAY_POCR_BSY_WMC_WIDTH               (1U)
415 #define FLEXRAY_POCR_BSY_WMC(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_POCR_BSY_WMC_SHIFT)) & FLEXRAY_POCR_BSY_WMC_MASK)
416 
417 #define FLEXRAY_POCR_ERC_AP_MASK                 (0x300U)
418 #define FLEXRAY_POCR_ERC_AP_SHIFT                (8U)
419 #define FLEXRAY_POCR_ERC_AP_WIDTH                (2U)
420 #define FLEXRAY_POCR_ERC_AP(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_POCR_ERC_AP_SHIFT)) & FLEXRAY_POCR_ERC_AP_MASK)
421 
422 #define FLEXRAY_POCR_EOC_AP_MASK                 (0xC00U)
423 #define FLEXRAY_POCR_EOC_AP_SHIFT                (10U)
424 #define FLEXRAY_POCR_EOC_AP_WIDTH                (2U)
425 #define FLEXRAY_POCR_EOC_AP(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_POCR_EOC_AP_SHIFT)) & FLEXRAY_POCR_EOC_AP_MASK)
426 
427 #define FLEXRAY_POCR_WME_MASK                    (0x8000U)
428 #define FLEXRAY_POCR_WME_SHIFT                   (15U)
429 #define FLEXRAY_POCR_WME_WIDTH                   (1U)
430 #define FLEXRAY_POCR_WME(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_POCR_WME_SHIFT)) & FLEXRAY_POCR_WME_MASK)
431 /*! @} */
432 
433 /*! @name GIFER - Global Interrupt Flag And Enable */
434 /*! @{ */
435 
436 #define FLEXRAY_GIFER_TBIE_MASK                  (0x1U)
437 #define FLEXRAY_GIFER_TBIE_SHIFT                 (0U)
438 #define FLEXRAY_GIFER_TBIE_WIDTH                 (1U)
439 #define FLEXRAY_GIFER_TBIE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_TBIE_SHIFT)) & FLEXRAY_GIFER_TBIE_MASK)
440 
441 #define FLEXRAY_GIFER_RBIE_MASK                  (0x2U)
442 #define FLEXRAY_GIFER_RBIE_SHIFT                 (1U)
443 #define FLEXRAY_GIFER_RBIE_WIDTH                 (1U)
444 #define FLEXRAY_GIFER_RBIE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_RBIE_SHIFT)) & FLEXRAY_GIFER_RBIE_MASK)
445 
446 #define FLEXRAY_GIFER_FAFAIE_MASK                (0x4U)
447 #define FLEXRAY_GIFER_FAFAIE_SHIFT               (2U)
448 #define FLEXRAY_GIFER_FAFAIE_WIDTH               (1U)
449 #define FLEXRAY_GIFER_FAFAIE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_FAFAIE_SHIFT)) & FLEXRAY_GIFER_FAFAIE_MASK)
450 
451 #define FLEXRAY_GIFER_FAFBIE_MASK                (0x8U)
452 #define FLEXRAY_GIFER_FAFBIE_SHIFT               (3U)
453 #define FLEXRAY_GIFER_FAFBIE_WIDTH               (1U)
454 #define FLEXRAY_GIFER_FAFBIE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_FAFBIE_SHIFT)) & FLEXRAY_GIFER_FAFBIE_MASK)
455 
456 #define FLEXRAY_GIFER_WUPIE_MASK                 (0x10U)
457 #define FLEXRAY_GIFER_WUPIE_SHIFT                (4U)
458 #define FLEXRAY_GIFER_WUPIE_WIDTH                (1U)
459 #define FLEXRAY_GIFER_WUPIE(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_WUPIE_SHIFT)) & FLEXRAY_GIFER_WUPIE_MASK)
460 
461 #define FLEXRAY_GIFER_CHIE_MASK                  (0x20U)
462 #define FLEXRAY_GIFER_CHIE_SHIFT                 (5U)
463 #define FLEXRAY_GIFER_CHIE_WIDTH                 (1U)
464 #define FLEXRAY_GIFER_CHIE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_CHIE_SHIFT)) & FLEXRAY_GIFER_CHIE_MASK)
465 
466 #define FLEXRAY_GIFER_PRIE_MASK                  (0x40U)
467 #define FLEXRAY_GIFER_PRIE_SHIFT                 (6U)
468 #define FLEXRAY_GIFER_PRIE_WIDTH                 (1U)
469 #define FLEXRAY_GIFER_PRIE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_PRIE_SHIFT)) & FLEXRAY_GIFER_PRIE_MASK)
470 
471 #define FLEXRAY_GIFER_MIE_MASK                   (0x80U)
472 #define FLEXRAY_GIFER_MIE_SHIFT                  (7U)
473 #define FLEXRAY_GIFER_MIE_WIDTH                  (1U)
474 #define FLEXRAY_GIFER_MIE(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_MIE_SHIFT)) & FLEXRAY_GIFER_MIE_MASK)
475 
476 #define FLEXRAY_GIFER_TBIF_MASK                  (0x100U)
477 #define FLEXRAY_GIFER_TBIF_SHIFT                 (8U)
478 #define FLEXRAY_GIFER_TBIF_WIDTH                 (1U)
479 #define FLEXRAY_GIFER_TBIF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_TBIF_SHIFT)) & FLEXRAY_GIFER_TBIF_MASK)
480 
481 #define FLEXRAY_GIFER_RBIF_MASK                  (0x200U)
482 #define FLEXRAY_GIFER_RBIF_SHIFT                 (9U)
483 #define FLEXRAY_GIFER_RBIF_WIDTH                 (1U)
484 #define FLEXRAY_GIFER_RBIF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_RBIF_SHIFT)) & FLEXRAY_GIFER_RBIF_MASK)
485 
486 #define FLEXRAY_GIFER_FAFAIF_MASK                (0x400U)
487 #define FLEXRAY_GIFER_FAFAIF_SHIFT               (10U)
488 #define FLEXRAY_GIFER_FAFAIF_WIDTH               (1U)
489 #define FLEXRAY_GIFER_FAFAIF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_FAFAIF_SHIFT)) & FLEXRAY_GIFER_FAFAIF_MASK)
490 
491 #define FLEXRAY_GIFER_FAFBIF_MASK                (0x800U)
492 #define FLEXRAY_GIFER_FAFBIF_SHIFT               (11U)
493 #define FLEXRAY_GIFER_FAFBIF_WIDTH               (1U)
494 #define FLEXRAY_GIFER_FAFBIF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_FAFBIF_SHIFT)) & FLEXRAY_GIFER_FAFBIF_MASK)
495 
496 #define FLEXRAY_GIFER_WUPIF_MASK                 (0x1000U)
497 #define FLEXRAY_GIFER_WUPIF_SHIFT                (12U)
498 #define FLEXRAY_GIFER_WUPIF_WIDTH                (1U)
499 #define FLEXRAY_GIFER_WUPIF(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_WUPIF_SHIFT)) & FLEXRAY_GIFER_WUPIF_MASK)
500 
501 #define FLEXRAY_GIFER_CHIF_MASK                  (0x2000U)
502 #define FLEXRAY_GIFER_CHIF_SHIFT                 (13U)
503 #define FLEXRAY_GIFER_CHIF_WIDTH                 (1U)
504 #define FLEXRAY_GIFER_CHIF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_CHIF_SHIFT)) & FLEXRAY_GIFER_CHIF_MASK)
505 
506 #define FLEXRAY_GIFER_PRIF_MASK                  (0x4000U)
507 #define FLEXRAY_GIFER_PRIF_SHIFT                 (14U)
508 #define FLEXRAY_GIFER_PRIF_WIDTH                 (1U)
509 #define FLEXRAY_GIFER_PRIF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_PRIF_SHIFT)) & FLEXRAY_GIFER_PRIF_MASK)
510 
511 #define FLEXRAY_GIFER_MIF_MASK                   (0x8000U)
512 #define FLEXRAY_GIFER_MIF_SHIFT                  (15U)
513 #define FLEXRAY_GIFER_MIF_WIDTH                  (1U)
514 #define FLEXRAY_GIFER_MIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_GIFER_MIF_SHIFT)) & FLEXRAY_GIFER_MIF_MASK)
515 /*! @} */
516 
517 /*! @name PIFR0 - Protocol Interrupt Flag 0 */
518 /*! @{ */
519 
520 #define FLEXRAY_PIFR0_CYS_IF_MASK                (0x1U)
521 #define FLEXRAY_PIFR0_CYS_IF_SHIFT               (0U)
522 #define FLEXRAY_PIFR0_CYS_IF_WIDTH               (1U)
523 #define FLEXRAY_PIFR0_CYS_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_CYS_IF_SHIFT)) & FLEXRAY_PIFR0_CYS_IF_MASK)
524 
525 #define FLEXRAY_PIFR0_TI1_IF_MASK                (0x2U)
526 #define FLEXRAY_PIFR0_TI1_IF_SHIFT               (1U)
527 #define FLEXRAY_PIFR0_TI1_IF_WIDTH               (1U)
528 #define FLEXRAY_PIFR0_TI1_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_TI1_IF_SHIFT)) & FLEXRAY_PIFR0_TI1_IF_MASK)
529 
530 #define FLEXRAY_PIFR0_TI2_IF_MASK                (0x4U)
531 #define FLEXRAY_PIFR0_TI2_IF_SHIFT               (2U)
532 #define FLEXRAY_PIFR0_TI2_IF_WIDTH               (1U)
533 #define FLEXRAY_PIFR0_TI2_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_TI2_IF_SHIFT)) & FLEXRAY_PIFR0_TI2_IF_MASK)
534 
535 #define FLEXRAY_PIFR0_TBVA_IF_MASK               (0x8U)
536 #define FLEXRAY_PIFR0_TBVA_IF_SHIFT              (3U)
537 #define FLEXRAY_PIFR0_TBVA_IF_WIDTH              (1U)
538 #define FLEXRAY_PIFR0_TBVA_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_TBVA_IF_SHIFT)) & FLEXRAY_PIFR0_TBVA_IF_MASK)
539 
540 #define FLEXRAY_PIFR0_TBVB_IF_MASK               (0x10U)
541 #define FLEXRAY_PIFR0_TBVB_IF_SHIFT              (4U)
542 #define FLEXRAY_PIFR0_TBVB_IF_WIDTH              (1U)
543 #define FLEXRAY_PIFR0_TBVB_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_TBVB_IF_SHIFT)) & FLEXRAY_PIFR0_TBVB_IF_MASK)
544 
545 #define FLEXRAY_PIFR0_LTXA_IF_MASK               (0x20U)
546 #define FLEXRAY_PIFR0_LTXA_IF_SHIFT              (5U)
547 #define FLEXRAY_PIFR0_LTXA_IF_WIDTH              (1U)
548 #define FLEXRAY_PIFR0_LTXA_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_LTXA_IF_SHIFT)) & FLEXRAY_PIFR0_LTXA_IF_MASK)
549 
550 #define FLEXRAY_PIFR0_LTXB_IF_MASK               (0x40U)
551 #define FLEXRAY_PIFR0_LTXB_IF_SHIFT              (6U)
552 #define FLEXRAY_PIFR0_LTXB_IF_WIDTH              (1U)
553 #define FLEXRAY_PIFR0_LTXB_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_LTXB_IF_SHIFT)) & FLEXRAY_PIFR0_LTXB_IF_MASK)
554 
555 #define FLEXRAY_PIFR0_MTX_IF_MASK                (0x80U)
556 #define FLEXRAY_PIFR0_MTX_IF_SHIFT               (7U)
557 #define FLEXRAY_PIFR0_MTX_IF_WIDTH               (1U)
558 #define FLEXRAY_PIFR0_MTX_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_MTX_IF_SHIFT)) & FLEXRAY_PIFR0_MTX_IF_MASK)
559 
560 #define FLEXRAY_PIFR0_MXS_IF_MASK                (0x100U)
561 #define FLEXRAY_PIFR0_MXS_IF_SHIFT               (8U)
562 #define FLEXRAY_PIFR0_MXS_IF_WIDTH               (1U)
563 #define FLEXRAY_PIFR0_MXS_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_MXS_IF_SHIFT)) & FLEXRAY_PIFR0_MXS_IF_MASK)
564 
565 #define FLEXRAY_PIFR0_CCL_IF_MASK                (0x200U)
566 #define FLEXRAY_PIFR0_CCL_IF_SHIFT               (9U)
567 #define FLEXRAY_PIFR0_CCL_IF_WIDTH               (1U)
568 #define FLEXRAY_PIFR0_CCL_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_CCL_IF_SHIFT)) & FLEXRAY_PIFR0_CCL_IF_MASK)
569 
570 #define FLEXRAY_PIFR0_MOC_IF_MASK                (0x400U)
571 #define FLEXRAY_PIFR0_MOC_IF_SHIFT               (10U)
572 #define FLEXRAY_PIFR0_MOC_IF_WIDTH               (1U)
573 #define FLEXRAY_PIFR0_MOC_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_MOC_IF_SHIFT)) & FLEXRAY_PIFR0_MOC_IF_MASK)
574 
575 #define FLEXRAY_PIFR0_MRC_IF_MASK                (0x800U)
576 #define FLEXRAY_PIFR0_MRC_IF_SHIFT               (11U)
577 #define FLEXRAY_PIFR0_MRC_IF_WIDTH               (1U)
578 #define FLEXRAY_PIFR0_MRC_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_MRC_IF_SHIFT)) & FLEXRAY_PIFR0_MRC_IF_MASK)
579 
580 #define FLEXRAY_PIFR0_CSA_IF_MASK                (0x1000U)
581 #define FLEXRAY_PIFR0_CSA_IF_SHIFT               (12U)
582 #define FLEXRAY_PIFR0_CSA_IF_WIDTH               (1U)
583 #define FLEXRAY_PIFR0_CSA_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_CSA_IF_SHIFT)) & FLEXRAY_PIFR0_CSA_IF_MASK)
584 
585 #define FLEXRAY_PIFR0_ILCF_IF_MASK               (0x2000U)
586 #define FLEXRAY_PIFR0_ILCF_IF_SHIFT              (13U)
587 #define FLEXRAY_PIFR0_ILCF_IF_WIDTH              (1U)
588 #define FLEXRAY_PIFR0_ILCF_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_ILCF_IF_SHIFT)) & FLEXRAY_PIFR0_ILCF_IF_MASK)
589 
590 #define FLEXRAY_PIFR0_INTL_IF_MASK               (0x4000U)
591 #define FLEXRAY_PIFR0_INTL_IF_SHIFT              (14U)
592 #define FLEXRAY_PIFR0_INTL_IF_WIDTH              (1U)
593 #define FLEXRAY_PIFR0_INTL_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_INTL_IF_SHIFT)) & FLEXRAY_PIFR0_INTL_IF_MASK)
594 
595 #define FLEXRAY_PIFR0_FATL_IF_MASK               (0x8000U)
596 #define FLEXRAY_PIFR0_FATL_IF_SHIFT              (15U)
597 #define FLEXRAY_PIFR0_FATL_IF_WIDTH              (1U)
598 #define FLEXRAY_PIFR0_FATL_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR0_FATL_IF_SHIFT)) & FLEXRAY_PIFR0_FATL_IF_MASK)
599 /*! @} */
600 
601 /*! @name PIFR1 - Protocol Interrupt Flag 1 */
602 /*! @{ */
603 
604 #define FLEXRAY_PIFR1_ODT_IF_MASK                (0x10U)
605 #define FLEXRAY_PIFR1_ODT_IF_SHIFT               (4U)
606 #define FLEXRAY_PIFR1_ODT_IF_WIDTH               (1U)
607 #define FLEXRAY_PIFR1_ODT_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_ODT_IF_SHIFT)) & FLEXRAY_PIFR1_ODT_IF_MASK)
608 
609 #define FLEXRAY_PIFR1_EVT_IF_MASK                (0x20U)
610 #define FLEXRAY_PIFR1_EVT_IF_SHIFT               (5U)
611 #define FLEXRAY_PIFR1_EVT_IF_WIDTH               (1U)
612 #define FLEXRAY_PIFR1_EVT_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_EVT_IF_SHIFT)) & FLEXRAY_PIFR1_EVT_IF_MASK)
613 
614 #define FLEXRAY_PIFR1_SSI0_IF_MASK               (0x100U)
615 #define FLEXRAY_PIFR1_SSI0_IF_SHIFT              (8U)
616 #define FLEXRAY_PIFR1_SSI0_IF_WIDTH              (1U)
617 #define FLEXRAY_PIFR1_SSI0_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_SSI0_IF_SHIFT)) & FLEXRAY_PIFR1_SSI0_IF_MASK)
618 
619 #define FLEXRAY_PIFR1_SSI1_IF_MASK               (0x200U)
620 #define FLEXRAY_PIFR1_SSI1_IF_SHIFT              (9U)
621 #define FLEXRAY_PIFR1_SSI1_IF_WIDTH              (1U)
622 #define FLEXRAY_PIFR1_SSI1_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_SSI1_IF_SHIFT)) & FLEXRAY_PIFR1_SSI1_IF_MASK)
623 
624 #define FLEXRAY_PIFR1_SSI2_IF_MASK               (0x400U)
625 #define FLEXRAY_PIFR1_SSI2_IF_SHIFT              (10U)
626 #define FLEXRAY_PIFR1_SSI2_IF_WIDTH              (1U)
627 #define FLEXRAY_PIFR1_SSI2_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_SSI2_IF_SHIFT)) & FLEXRAY_PIFR1_SSI2_IF_MASK)
628 
629 #define FLEXRAY_PIFR1_SSI3_IF_MASK               (0x800U)
630 #define FLEXRAY_PIFR1_SSI3_IF_SHIFT              (11U)
631 #define FLEXRAY_PIFR1_SSI3_IF_WIDTH              (1U)
632 #define FLEXRAY_PIFR1_SSI3_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_SSI3_IF_SHIFT)) & FLEXRAY_PIFR1_SSI3_IF_MASK)
633 
634 #define FLEXRAY_PIFR1_PSC_IF_MASK                (0x1000U)
635 #define FLEXRAY_PIFR1_PSC_IF_SHIFT               (12U)
636 #define FLEXRAY_PIFR1_PSC_IF_WIDTH               (1U)
637 #define FLEXRAY_PIFR1_PSC_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_PSC_IF_SHIFT)) & FLEXRAY_PIFR1_PSC_IF_MASK)
638 
639 #define FLEXRAY_PIFR1_PECF_IF_MASK               (0x2000U)
640 #define FLEXRAY_PIFR1_PECF_IF_SHIFT              (13U)
641 #define FLEXRAY_PIFR1_PECF_IF_WIDTH              (1U)
642 #define FLEXRAY_PIFR1_PECF_IF(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_PECF_IF_SHIFT)) & FLEXRAY_PIFR1_PECF_IF_MASK)
643 
644 #define FLEXRAY_PIFR1_IPC_IF_MASK                (0x4000U)
645 #define FLEXRAY_PIFR1_IPC_IF_SHIFT               (14U)
646 #define FLEXRAY_PIFR1_IPC_IF_WIDTH               (1U)
647 #define FLEXRAY_PIFR1_IPC_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_IPC_IF_SHIFT)) & FLEXRAY_PIFR1_IPC_IF_MASK)
648 
649 #define FLEXRAY_PIFR1_EMC_IF_MASK                (0x8000U)
650 #define FLEXRAY_PIFR1_EMC_IF_SHIFT               (15U)
651 #define FLEXRAY_PIFR1_EMC_IF_WIDTH               (1U)
652 #define FLEXRAY_PIFR1_EMC_IF(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIFR1_EMC_IF_SHIFT)) & FLEXRAY_PIFR1_EMC_IF_MASK)
653 /*! @} */
654 
655 /*! @name PIER0 - Protocol Interrupt Enable 0 */
656 /*! @{ */
657 
658 #define FLEXRAY_PIER0_CYS_IE_MASK                (0x1U)
659 #define FLEXRAY_PIER0_CYS_IE_SHIFT               (0U)
660 #define FLEXRAY_PIER0_CYS_IE_WIDTH               (1U)
661 #define FLEXRAY_PIER0_CYS_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_CYS_IE_SHIFT)) & FLEXRAY_PIER0_CYS_IE_MASK)
662 
663 #define FLEXRAY_PIER0_TI1_IE_MASK                (0x2U)
664 #define FLEXRAY_PIER0_TI1_IE_SHIFT               (1U)
665 #define FLEXRAY_PIER0_TI1_IE_WIDTH               (1U)
666 #define FLEXRAY_PIER0_TI1_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_TI1_IE_SHIFT)) & FLEXRAY_PIER0_TI1_IE_MASK)
667 
668 #define FLEXRAY_PIER0_TI2_IE_MASK                (0x4U)
669 #define FLEXRAY_PIER0_TI2_IE_SHIFT               (2U)
670 #define FLEXRAY_PIER0_TI2_IE_WIDTH               (1U)
671 #define FLEXRAY_PIER0_TI2_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_TI2_IE_SHIFT)) & FLEXRAY_PIER0_TI2_IE_MASK)
672 
673 #define FLEXRAY_PIER0_TBVA_IE_MASK               (0x8U)
674 #define FLEXRAY_PIER0_TBVA_IE_SHIFT              (3U)
675 #define FLEXRAY_PIER0_TBVA_IE_WIDTH              (1U)
676 #define FLEXRAY_PIER0_TBVA_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_TBVA_IE_SHIFT)) & FLEXRAY_PIER0_TBVA_IE_MASK)
677 
678 #define FLEXRAY_PIER0_TBVB_IE_MASK               (0x10U)
679 #define FLEXRAY_PIER0_TBVB_IE_SHIFT              (4U)
680 #define FLEXRAY_PIER0_TBVB_IE_WIDTH              (1U)
681 #define FLEXRAY_PIER0_TBVB_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_TBVB_IE_SHIFT)) & FLEXRAY_PIER0_TBVB_IE_MASK)
682 
683 #define FLEXRAY_PIER0_LTXA_IE_MASK               (0x20U)
684 #define FLEXRAY_PIER0_LTXA_IE_SHIFT              (5U)
685 #define FLEXRAY_PIER0_LTXA_IE_WIDTH              (1U)
686 #define FLEXRAY_PIER0_LTXA_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_LTXA_IE_SHIFT)) & FLEXRAY_PIER0_LTXA_IE_MASK)
687 
688 #define FLEXRAY_PIER0_LTXB_IE_MASK               (0x40U)
689 #define FLEXRAY_PIER0_LTXB_IE_SHIFT              (6U)
690 #define FLEXRAY_PIER0_LTXB_IE_WIDTH              (1U)
691 #define FLEXRAY_PIER0_LTXB_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_LTXB_IE_SHIFT)) & FLEXRAY_PIER0_LTXB_IE_MASK)
692 
693 #define FLEXRAY_PIER0_MTX_IE_MASK                (0x80U)
694 #define FLEXRAY_PIER0_MTX_IE_SHIFT               (7U)
695 #define FLEXRAY_PIER0_MTX_IE_WIDTH               (1U)
696 #define FLEXRAY_PIER0_MTX_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_MTX_IE_SHIFT)) & FLEXRAY_PIER0_MTX_IE_MASK)
697 
698 #define FLEXRAY_PIER0_MXS_IE_MASK                (0x100U)
699 #define FLEXRAY_PIER0_MXS_IE_SHIFT               (8U)
700 #define FLEXRAY_PIER0_MXS_IE_WIDTH               (1U)
701 #define FLEXRAY_PIER0_MXS_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_MXS_IE_SHIFT)) & FLEXRAY_PIER0_MXS_IE_MASK)
702 
703 #define FLEXRAY_PIER0_CCL_IE_MASK                (0x200U)
704 #define FLEXRAY_PIER0_CCL_IE_SHIFT               (9U)
705 #define FLEXRAY_PIER0_CCL_IE_WIDTH               (1U)
706 #define FLEXRAY_PIER0_CCL_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_CCL_IE_SHIFT)) & FLEXRAY_PIER0_CCL_IE_MASK)
707 
708 #define FLEXRAY_PIER0_MOC_IE_MASK                (0x400U)
709 #define FLEXRAY_PIER0_MOC_IE_SHIFT               (10U)
710 #define FLEXRAY_PIER0_MOC_IE_WIDTH               (1U)
711 #define FLEXRAY_PIER0_MOC_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_MOC_IE_SHIFT)) & FLEXRAY_PIER0_MOC_IE_MASK)
712 
713 #define FLEXRAY_PIER0_MRC_IE_MASK                (0x800U)
714 #define FLEXRAY_PIER0_MRC_IE_SHIFT               (11U)
715 #define FLEXRAY_PIER0_MRC_IE_WIDTH               (1U)
716 #define FLEXRAY_PIER0_MRC_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_MRC_IE_SHIFT)) & FLEXRAY_PIER0_MRC_IE_MASK)
717 
718 #define FLEXRAY_PIER0_CSA_IE_MASK                (0x1000U)
719 #define FLEXRAY_PIER0_CSA_IE_SHIFT               (12U)
720 #define FLEXRAY_PIER0_CSA_IE_WIDTH               (1U)
721 #define FLEXRAY_PIER0_CSA_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_CSA_IE_SHIFT)) & FLEXRAY_PIER0_CSA_IE_MASK)
722 
723 #define FLEXRAY_PIER0_ILCF_IE_MASK               (0x2000U)
724 #define FLEXRAY_PIER0_ILCF_IE_SHIFT              (13U)
725 #define FLEXRAY_PIER0_ILCF_IE_WIDTH              (1U)
726 #define FLEXRAY_PIER0_ILCF_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_ILCF_IE_SHIFT)) & FLEXRAY_PIER0_ILCF_IE_MASK)
727 
728 #define FLEXRAY_PIER0_INTL_IE_MASK               (0x4000U)
729 #define FLEXRAY_PIER0_INTL_IE_SHIFT              (14U)
730 #define FLEXRAY_PIER0_INTL_IE_WIDTH              (1U)
731 #define FLEXRAY_PIER0_INTL_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_INTL_IE_SHIFT)) & FLEXRAY_PIER0_INTL_IE_MASK)
732 
733 #define FLEXRAY_PIER0_FATL_IE_MASK               (0x8000U)
734 #define FLEXRAY_PIER0_FATL_IE_SHIFT              (15U)
735 #define FLEXRAY_PIER0_FATL_IE_WIDTH              (1U)
736 #define FLEXRAY_PIER0_FATL_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER0_FATL_IE_SHIFT)) & FLEXRAY_PIER0_FATL_IE_MASK)
737 /*! @} */
738 
739 /*! @name PIER1 - Protocol Interrupt Enable 1 */
740 /*! @{ */
741 
742 #define FLEXRAY_PIER1_ODT_IE_MASK                (0x10U)
743 #define FLEXRAY_PIER1_ODT_IE_SHIFT               (4U)
744 #define FLEXRAY_PIER1_ODT_IE_WIDTH               (1U)
745 #define FLEXRAY_PIER1_ODT_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_ODT_IE_SHIFT)) & FLEXRAY_PIER1_ODT_IE_MASK)
746 
747 #define FLEXRAY_PIER1_EVT_IE_MASK                (0x20U)
748 #define FLEXRAY_PIER1_EVT_IE_SHIFT               (5U)
749 #define FLEXRAY_PIER1_EVT_IE_WIDTH               (1U)
750 #define FLEXRAY_PIER1_EVT_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_EVT_IE_SHIFT)) & FLEXRAY_PIER1_EVT_IE_MASK)
751 
752 #define FLEXRAY_PIER1_SSI0_IE_MASK               (0x100U)
753 #define FLEXRAY_PIER1_SSI0_IE_SHIFT              (8U)
754 #define FLEXRAY_PIER1_SSI0_IE_WIDTH              (1U)
755 #define FLEXRAY_PIER1_SSI0_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_SSI0_IE_SHIFT)) & FLEXRAY_PIER1_SSI0_IE_MASK)
756 
757 #define FLEXRAY_PIER1_SSI1_IE_MASK               (0x200U)
758 #define FLEXRAY_PIER1_SSI1_IE_SHIFT              (9U)
759 #define FLEXRAY_PIER1_SSI1_IE_WIDTH              (1U)
760 #define FLEXRAY_PIER1_SSI1_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_SSI1_IE_SHIFT)) & FLEXRAY_PIER1_SSI1_IE_MASK)
761 
762 #define FLEXRAY_PIER1_SSI2_IE_MASK               (0x400U)
763 #define FLEXRAY_PIER1_SSI2_IE_SHIFT              (10U)
764 #define FLEXRAY_PIER1_SSI2_IE_WIDTH              (1U)
765 #define FLEXRAY_PIER1_SSI2_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_SSI2_IE_SHIFT)) & FLEXRAY_PIER1_SSI2_IE_MASK)
766 
767 #define FLEXRAY_PIER1_SSI3_IE_MASK               (0x800U)
768 #define FLEXRAY_PIER1_SSI3_IE_SHIFT              (11U)
769 #define FLEXRAY_PIER1_SSI3_IE_WIDTH              (1U)
770 #define FLEXRAY_PIER1_SSI3_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_SSI3_IE_SHIFT)) & FLEXRAY_PIER1_SSI3_IE_MASK)
771 
772 #define FLEXRAY_PIER1_PSC_IE_MASK                (0x1000U)
773 #define FLEXRAY_PIER1_PSC_IE_SHIFT               (12U)
774 #define FLEXRAY_PIER1_PSC_IE_WIDTH               (1U)
775 #define FLEXRAY_PIER1_PSC_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_PSC_IE_SHIFT)) & FLEXRAY_PIER1_PSC_IE_MASK)
776 
777 #define FLEXRAY_PIER1_PECF_IE_MASK               (0x2000U)
778 #define FLEXRAY_PIER1_PECF_IE_SHIFT              (13U)
779 #define FLEXRAY_PIER1_PECF_IE_WIDTH              (1U)
780 #define FLEXRAY_PIER1_PECF_IE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_PECF_IE_SHIFT)) & FLEXRAY_PIER1_PECF_IE_MASK)
781 
782 #define FLEXRAY_PIER1_IPC_IE_MASK                (0x4000U)
783 #define FLEXRAY_PIER1_IPC_IE_SHIFT               (14U)
784 #define FLEXRAY_PIER1_IPC_IE_WIDTH               (1U)
785 #define FLEXRAY_PIER1_IPC_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_IPC_IE_SHIFT)) & FLEXRAY_PIER1_IPC_IE_MASK)
786 
787 #define FLEXRAY_PIER1_EMC_IE_MASK                (0x8000U)
788 #define FLEXRAY_PIER1_EMC_IE_SHIFT               (15U)
789 #define FLEXRAY_PIER1_EMC_IE_WIDTH               (1U)
790 #define FLEXRAY_PIER1_EMC_IE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PIER1_EMC_IE_SHIFT)) & FLEXRAY_PIER1_EMC_IE_MASK)
791 /*! @} */
792 
793 /*! @name CHIERFR - CHI Error Flag */
794 /*! @{ */
795 
796 #define FLEXRAY_CHIERFR_ILSA_EF_MASK             (0x1U)
797 #define FLEXRAY_CHIERFR_ILSA_EF_SHIFT            (0U)
798 #define FLEXRAY_CHIERFR_ILSA_EF_WIDTH            (1U)
799 #define FLEXRAY_CHIERFR_ILSA_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_ILSA_EF_SHIFT)) & FLEXRAY_CHIERFR_ILSA_EF_MASK)
800 
801 #define FLEXRAY_CHIERFR_NMF_EF_MASK              (0x2U)
802 #define FLEXRAY_CHIERFR_NMF_EF_SHIFT             (1U)
803 #define FLEXRAY_CHIERFR_NMF_EF_WIDTH             (1U)
804 #define FLEXRAY_CHIERFR_NMF_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_NMF_EF_SHIFT)) & FLEXRAY_CHIERFR_NMF_EF_MASK)
805 
806 #define FLEXRAY_CHIERFR_NML_EF_MASK              (0x4U)
807 #define FLEXRAY_CHIERFR_NML_EF_SHIFT             (2U)
808 #define FLEXRAY_CHIERFR_NML_EF_WIDTH             (1U)
809 #define FLEXRAY_CHIERFR_NML_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_NML_EF_SHIFT)) & FLEXRAY_CHIERFR_NML_EF_MASK)
810 
811 #define FLEXRAY_CHIERFR_SPL_EF_MASK              (0x8U)
812 #define FLEXRAY_CHIERFR_SPL_EF_SHIFT             (3U)
813 #define FLEXRAY_CHIERFR_SPL_EF_WIDTH             (1U)
814 #define FLEXRAY_CHIERFR_SPL_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_SPL_EF_SHIFT)) & FLEXRAY_CHIERFR_SPL_EF_MASK)
815 
816 #define FLEXRAY_CHIERFR_DPL_EF_MASK              (0x10U)
817 #define FLEXRAY_CHIERFR_DPL_EF_SHIFT             (4U)
818 #define FLEXRAY_CHIERFR_DPL_EF_WIDTH             (1U)
819 #define FLEXRAY_CHIERFR_DPL_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_DPL_EF_SHIFT)) & FLEXRAY_CHIERFR_DPL_EF_MASK)
820 
821 #define FLEXRAY_CHIERFR_FID_EF_MASK              (0x20U)
822 #define FLEXRAY_CHIERFR_FID_EF_SHIFT             (5U)
823 #define FLEXRAY_CHIERFR_FID_EF_WIDTH             (1U)
824 #define FLEXRAY_CHIERFR_FID_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_FID_EF_SHIFT)) & FLEXRAY_CHIERFR_FID_EF_MASK)
825 
826 #define FLEXRAY_CHIERFR_SBCF_EF_MASK             (0x40U)
827 #define FLEXRAY_CHIERFR_SBCF_EF_SHIFT            (6U)
828 #define FLEXRAY_CHIERFR_SBCF_EF_WIDTH            (1U)
829 #define FLEXRAY_CHIERFR_SBCF_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_SBCF_EF_SHIFT)) & FLEXRAY_CHIERFR_SBCF_EF_MASK)
830 
831 #define FLEXRAY_CHIERFR_LCK_EF_MASK              (0x100U)
832 #define FLEXRAY_CHIERFR_LCK_EF_SHIFT             (8U)
833 #define FLEXRAY_CHIERFR_LCK_EF_WIDTH             (1U)
834 #define FLEXRAY_CHIERFR_LCK_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_LCK_EF_SHIFT)) & FLEXRAY_CHIERFR_LCK_EF_MASK)
835 
836 #define FLEXRAY_CHIERFR_MBU_EF_MASK              (0x200U)
837 #define FLEXRAY_CHIERFR_MBU_EF_SHIFT             (9U)
838 #define FLEXRAY_CHIERFR_MBU_EF_WIDTH             (1U)
839 #define FLEXRAY_CHIERFR_MBU_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_MBU_EF_SHIFT)) & FLEXRAY_CHIERFR_MBU_EF_MASK)
840 
841 #define FLEXRAY_CHIERFR_MBS_EF_MASK              (0x400U)
842 #define FLEXRAY_CHIERFR_MBS_EF_SHIFT             (10U)
843 #define FLEXRAY_CHIERFR_MBS_EF_WIDTH             (1U)
844 #define FLEXRAY_CHIERFR_MBS_EF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_MBS_EF_SHIFT)) & FLEXRAY_CHIERFR_MBS_EF_MASK)
845 
846 #define FLEXRAY_CHIERFR_FOVA_EF_MASK             (0x800U)
847 #define FLEXRAY_CHIERFR_FOVA_EF_SHIFT            (11U)
848 #define FLEXRAY_CHIERFR_FOVA_EF_WIDTH            (1U)
849 #define FLEXRAY_CHIERFR_FOVA_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_FOVA_EF_SHIFT)) & FLEXRAY_CHIERFR_FOVA_EF_MASK)
850 
851 #define FLEXRAY_CHIERFR_FOVB_EF_MASK             (0x1000U)
852 #define FLEXRAY_CHIERFR_FOVB_EF_SHIFT            (12U)
853 #define FLEXRAY_CHIERFR_FOVB_EF_WIDTH            (1U)
854 #define FLEXRAY_CHIERFR_FOVB_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_FOVB_EF_SHIFT)) & FLEXRAY_CHIERFR_FOVB_EF_MASK)
855 
856 #define FLEXRAY_CHIERFR_PCMI_EF_MASK             (0x2000U)
857 #define FLEXRAY_CHIERFR_PCMI_EF_SHIFT            (13U)
858 #define FLEXRAY_CHIERFR_PCMI_EF_WIDTH            (1U)
859 #define FLEXRAY_CHIERFR_PCMI_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_PCMI_EF_SHIFT)) & FLEXRAY_CHIERFR_PCMI_EF_MASK)
860 
861 #define FLEXRAY_CHIERFR_FRLA_EF_MASK             (0x4000U)
862 #define FLEXRAY_CHIERFR_FRLA_EF_SHIFT            (14U)
863 #define FLEXRAY_CHIERFR_FRLA_EF_WIDTH            (1U)
864 #define FLEXRAY_CHIERFR_FRLA_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_FRLA_EF_SHIFT)) & FLEXRAY_CHIERFR_FRLA_EF_MASK)
865 
866 #define FLEXRAY_CHIERFR_FRLB_EF_MASK             (0x8000U)
867 #define FLEXRAY_CHIERFR_FRLB_EF_SHIFT            (15U)
868 #define FLEXRAY_CHIERFR_FRLB_EF_WIDTH            (1U)
869 #define FLEXRAY_CHIERFR_FRLB_EF(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CHIERFR_FRLB_EF_SHIFT)) & FLEXRAY_CHIERFR_FRLB_EF_MASK)
870 /*! @} */
871 
872 /*! @name MBIVEC - MB Interrupt Vector */
873 /*! @{ */
874 
875 #define FLEXRAY_MBIVEC_RBIVEC_MASK               (0xFFU)
876 #define FLEXRAY_MBIVEC_RBIVEC_SHIFT              (0U)
877 #define FLEXRAY_MBIVEC_RBIVEC_WIDTH              (8U)
878 #define FLEXRAY_MBIVEC_RBIVEC(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBIVEC_RBIVEC_SHIFT)) & FLEXRAY_MBIVEC_RBIVEC_MASK)
879 
880 #define FLEXRAY_MBIVEC_TBIVEC_MASK               (0xFF00U)
881 #define FLEXRAY_MBIVEC_TBIVEC_SHIFT              (8U)
882 #define FLEXRAY_MBIVEC_TBIVEC_WIDTH              (8U)
883 #define FLEXRAY_MBIVEC_TBIVEC(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBIVEC_TBIVEC_SHIFT)) & FLEXRAY_MBIVEC_TBIVEC_MASK)
884 /*! @} */
885 
886 /*! @name CASERCR - Channel A Status Error Counter Register */
887 /*! @{ */
888 
889 #define FLEXRAY_CASERCR_CHAERSCNT_MASK           (0xFFFFU)
890 #define FLEXRAY_CASERCR_CHAERSCNT_SHIFT          (0U)
891 #define FLEXRAY_CASERCR_CHAERSCNT_WIDTH          (16U)
892 #define FLEXRAY_CASERCR_CHAERSCNT(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CASERCR_CHAERSCNT_SHIFT)) & FLEXRAY_CASERCR_CHAERSCNT_MASK)
893 /*! @} */
894 
895 /*! @name CBSERCR - Channel B Status Error Counter */
896 /*! @{ */
897 
898 #define FLEXRAY_CBSERCR_CHBERSCNT_MASK           (0xFFFFU)
899 #define FLEXRAY_CBSERCR_CHBERSCNT_SHIFT          (0U)
900 #define FLEXRAY_CBSERCR_CHBERSCNT_WIDTH          (16U)
901 #define FLEXRAY_CBSERCR_CHBERSCNT(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CBSERCR_CHBERSCNT_SHIFT)) & FLEXRAY_CBSERCR_CHBERSCNT_MASK)
902 /*! @} */
903 
904 /*! @name PSR0 - Protocol Status 0 */
905 /*! @{ */
906 
907 #define FLEXRAY_PSR0_WAKEUPSTATUS_MASK           (0x7U)
908 #define FLEXRAY_PSR0_WAKEUPSTATUS_SHIFT          (0U)
909 #define FLEXRAY_PSR0_WAKEUPSTATUS_WIDTH          (3U)
910 #define FLEXRAY_PSR0_WAKEUPSTATUS(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR0_WAKEUPSTATUS_SHIFT)) & FLEXRAY_PSR0_WAKEUPSTATUS_MASK)
911 
912 #define FLEXRAY_PSR0_STARTUPSTATE_MASK           (0xF0U)
913 #define FLEXRAY_PSR0_STARTUPSTATE_SHIFT          (4U)
914 #define FLEXRAY_PSR0_STARTUPSTATE_WIDTH          (4U)
915 #define FLEXRAY_PSR0_STARTUPSTATE(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR0_STARTUPSTATE_SHIFT)) & FLEXRAY_PSR0_STARTUPSTATE_MASK)
916 
917 #define FLEXRAY_PSR0_PROTSTATE_MASK              (0x700U)
918 #define FLEXRAY_PSR0_PROTSTATE_SHIFT             (8U)
919 #define FLEXRAY_PSR0_PROTSTATE_WIDTH             (3U)
920 #define FLEXRAY_PSR0_PROTSTATE(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR0_PROTSTATE_SHIFT)) & FLEXRAY_PSR0_PROTSTATE_MASK)
921 
922 #define FLEXRAY_PSR0_SLOTMODE_MASK               (0x3000U)
923 #define FLEXRAY_PSR0_SLOTMODE_SHIFT              (12U)
924 #define FLEXRAY_PSR0_SLOTMODE_WIDTH              (2U)
925 #define FLEXRAY_PSR0_SLOTMODE(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR0_SLOTMODE_SHIFT)) & FLEXRAY_PSR0_SLOTMODE_MASK)
926 
927 #define FLEXRAY_PSR0_ERRMODE_MASK                (0xC000U)
928 #define FLEXRAY_PSR0_ERRMODE_SHIFT               (14U)
929 #define FLEXRAY_PSR0_ERRMODE_WIDTH               (2U)
930 #define FLEXRAY_PSR0_ERRMODE(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR0_ERRMODE_SHIFT)) & FLEXRAY_PSR0_ERRMODE_MASK)
931 /*! @} */
932 
933 /*! @name PSR1 - Protocol Status 1 */
934 /*! @{ */
935 
936 #define FLEXRAY_PSR1_APTAC_MASK                  (0x1FU)
937 #define FLEXRAY_PSR1_APTAC_SHIFT                 (0U)
938 #define FLEXRAY_PSR1_APTAC_WIDTH                 (5U)
939 #define FLEXRAY_PSR1_APTAC(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_APTAC_SHIFT)) & FLEXRAY_PSR1_APTAC_MASK)
940 
941 #define FLEXRAY_PSR1_FRZ_MASK                    (0x20U)
942 #define FLEXRAY_PSR1_FRZ_SHIFT                   (5U)
943 #define FLEXRAY_PSR1_FRZ_WIDTH                   (1U)
944 #define FLEXRAY_PSR1_FRZ(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_FRZ_SHIFT)) & FLEXRAY_PSR1_FRZ_MASK)
945 
946 #define FLEXRAY_PSR1_HHR_MASK                    (0x40U)
947 #define FLEXRAY_PSR1_HHR_SHIFT                   (6U)
948 #define FLEXRAY_PSR1_HHR_WIDTH                   (1U)
949 #define FLEXRAY_PSR1_HHR(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_HHR_SHIFT)) & FLEXRAY_PSR1_HHR_MASK)
950 
951 #define FLEXRAY_PSR1_CPN_MASK                    (0x80U)
952 #define FLEXRAY_PSR1_CPN_SHIFT                   (7U)
953 #define FLEXRAY_PSR1_CPN_WIDTH                   (1U)
954 #define FLEXRAY_PSR1_CPN(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_CPN_SHIFT)) & FLEXRAY_PSR1_CPN_MASK)
955 
956 #define FLEXRAY_PSR1_REMCSAT_MASK                (0x1F00U)
957 #define FLEXRAY_PSR1_REMCSAT_SHIFT               (8U)
958 #define FLEXRAY_PSR1_REMCSAT_WIDTH               (5U)
959 #define FLEXRAY_PSR1_REMCSAT(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_REMCSAT_SHIFT)) & FLEXRAY_PSR1_REMCSAT_MASK)
960 
961 #define FLEXRAY_PSR1_CSP_MASK                    (0x4000U)
962 #define FLEXRAY_PSR1_CSP_SHIFT                   (14U)
963 #define FLEXRAY_PSR1_CSP_WIDTH                   (1U)
964 #define FLEXRAY_PSR1_CSP(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_CSP_SHIFT)) & FLEXRAY_PSR1_CSP_MASK)
965 
966 #define FLEXRAY_PSR1_CSAA_MASK                   (0x8000U)
967 #define FLEXRAY_PSR1_CSAA_SHIFT                  (15U)
968 #define FLEXRAY_PSR1_CSAA_WIDTH                  (1U)
969 #define FLEXRAY_PSR1_CSAA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR1_CSAA_SHIFT)) & FLEXRAY_PSR1_CSAA_MASK)
970 /*! @} */
971 
972 /*! @name PSR2 - Protocol Status 2 */
973 /*! @{ */
974 
975 #define FLEXRAY_PSR2_CKCORFCNT_MASK              (0xFU)
976 #define FLEXRAY_PSR2_CKCORFCNT_SHIFT             (0U)
977 #define FLEXRAY_PSR2_CKCORFCNT_WIDTH             (4U)
978 #define FLEXRAY_PSR2_CKCORFCNT(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_CKCORFCNT_SHIFT)) & FLEXRAY_PSR2_CKCORFCNT_MASK)
979 
980 #define FLEXRAY_PSR2_MTA_MASK                    (0x10U)
981 #define FLEXRAY_PSR2_MTA_SHIFT                   (4U)
982 #define FLEXRAY_PSR2_MTA_WIDTH                   (1U)
983 #define FLEXRAY_PSR2_MTA(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_MTA_SHIFT)) & FLEXRAY_PSR2_MTA_MASK)
984 
985 #define FLEXRAY_PSR2_SSEA_MASK                   (0x20U)
986 #define FLEXRAY_PSR2_SSEA_SHIFT                  (5U)
987 #define FLEXRAY_PSR2_SSEA_WIDTH                  (1U)
988 #define FLEXRAY_PSR2_SSEA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_SSEA_SHIFT)) & FLEXRAY_PSR2_SSEA_MASK)
989 
990 #define FLEXRAY_PSR2_SBVA_MASK                   (0x40U)
991 #define FLEXRAY_PSR2_SBVA_SHIFT                  (6U)
992 #define FLEXRAY_PSR2_SBVA_WIDTH                  (1U)
993 #define FLEXRAY_PSR2_SBVA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_SBVA_SHIFT)) & FLEXRAY_PSR2_SBVA_MASK)
994 
995 #define FLEXRAY_PSR2_STCA_MASK                   (0x80U)
996 #define FLEXRAY_PSR2_STCA_SHIFT                  (7U)
997 #define FLEXRAY_PSR2_STCA_WIDTH                  (1U)
998 #define FLEXRAY_PSR2_STCA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_STCA_SHIFT)) & FLEXRAY_PSR2_STCA_MASK)
999 
1000 #define FLEXRAY_PSR2_NSEA_MASK                   (0x100U)
1001 #define FLEXRAY_PSR2_NSEA_SHIFT                  (8U)
1002 #define FLEXRAY_PSR2_NSEA_WIDTH                  (1U)
1003 #define FLEXRAY_PSR2_NSEA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_NSEA_SHIFT)) & FLEXRAY_PSR2_NSEA_MASK)
1004 
1005 #define FLEXRAY_PSR2_NBVA_MASK                   (0x200U)
1006 #define FLEXRAY_PSR2_NBVA_SHIFT                  (9U)
1007 #define FLEXRAY_PSR2_NBVA_WIDTH                  (1U)
1008 #define FLEXRAY_PSR2_NBVA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_NBVA_SHIFT)) & FLEXRAY_PSR2_NBVA_MASK)
1009 
1010 #define FLEXRAY_PSR2_MTB_MASK                    (0x400U)
1011 #define FLEXRAY_PSR2_MTB_SHIFT                   (10U)
1012 #define FLEXRAY_PSR2_MTB_WIDTH                   (1U)
1013 #define FLEXRAY_PSR2_MTB(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_MTB_SHIFT)) & FLEXRAY_PSR2_MTB_MASK)
1014 
1015 #define FLEXRAY_PSR2_SSEB_MASK                   (0x800U)
1016 #define FLEXRAY_PSR2_SSEB_SHIFT                  (11U)
1017 #define FLEXRAY_PSR2_SSEB_WIDTH                  (1U)
1018 #define FLEXRAY_PSR2_SSEB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_SSEB_SHIFT)) & FLEXRAY_PSR2_SSEB_MASK)
1019 
1020 #define FLEXRAY_PSR2_SBVB_MASK                   (0x1000U)
1021 #define FLEXRAY_PSR2_SBVB_SHIFT                  (12U)
1022 #define FLEXRAY_PSR2_SBVB_WIDTH                  (1U)
1023 #define FLEXRAY_PSR2_SBVB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_SBVB_SHIFT)) & FLEXRAY_PSR2_SBVB_MASK)
1024 
1025 #define FLEXRAY_PSR2_STCB_MASK                   (0x2000U)
1026 #define FLEXRAY_PSR2_STCB_SHIFT                  (13U)
1027 #define FLEXRAY_PSR2_STCB_WIDTH                  (1U)
1028 #define FLEXRAY_PSR2_STCB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_STCB_SHIFT)) & FLEXRAY_PSR2_STCB_MASK)
1029 
1030 #define FLEXRAY_PSR2_NSEB_MASK                   (0x4000U)
1031 #define FLEXRAY_PSR2_NSEB_SHIFT                  (14U)
1032 #define FLEXRAY_PSR2_NSEB_WIDTH                  (1U)
1033 #define FLEXRAY_PSR2_NSEB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_NSEB_SHIFT)) & FLEXRAY_PSR2_NSEB_MASK)
1034 
1035 #define FLEXRAY_PSR2_NBVB_MASK                   (0x8000U)
1036 #define FLEXRAY_PSR2_NBVB_SHIFT                  (15U)
1037 #define FLEXRAY_PSR2_NBVB_WIDTH                  (1U)
1038 #define FLEXRAY_PSR2_NBVB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR2_NBVB_SHIFT)) & FLEXRAY_PSR2_NBVB_MASK)
1039 /*! @} */
1040 
1041 /*! @name PSR3 - Protocol Status 3 */
1042 /*! @{ */
1043 
1044 #define FLEXRAY_PSR3_AVFA_MASK                   (0x1U)
1045 #define FLEXRAY_PSR3_AVFA_SHIFT                  (0U)
1046 #define FLEXRAY_PSR3_AVFA_WIDTH                  (1U)
1047 #define FLEXRAY_PSR3_AVFA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_AVFA_SHIFT)) & FLEXRAY_PSR3_AVFA_MASK)
1048 
1049 #define FLEXRAY_PSR3_ASEA_MASK                   (0x2U)
1050 #define FLEXRAY_PSR3_ASEA_SHIFT                  (1U)
1051 #define FLEXRAY_PSR3_ASEA_WIDTH                  (1U)
1052 #define FLEXRAY_PSR3_ASEA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ASEA_SHIFT)) & FLEXRAY_PSR3_ASEA_MASK)
1053 
1054 #define FLEXRAY_PSR3_ACEA_MASK                   (0x4U)
1055 #define FLEXRAY_PSR3_ACEA_SHIFT                  (2U)
1056 #define FLEXRAY_PSR3_ACEA_WIDTH                  (1U)
1057 #define FLEXRAY_PSR3_ACEA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ACEA_SHIFT)) & FLEXRAY_PSR3_ACEA_MASK)
1058 
1059 #define FLEXRAY_PSR3_AACA_MASK                   (0x8U)
1060 #define FLEXRAY_PSR3_AACA_SHIFT                  (3U)
1061 #define FLEXRAY_PSR3_AACA_WIDTH                  (1U)
1062 #define FLEXRAY_PSR3_AACA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_AACA_SHIFT)) & FLEXRAY_PSR3_AACA_MASK)
1063 
1064 #define FLEXRAY_PSR3_ABVA_MASK                   (0x10U)
1065 #define FLEXRAY_PSR3_ABVA_SHIFT                  (4U)
1066 #define FLEXRAY_PSR3_ABVA_WIDTH                  (1U)
1067 #define FLEXRAY_PSR3_ABVA(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ABVA_SHIFT)) & FLEXRAY_PSR3_ABVA_MASK)
1068 
1069 #define FLEXRAY_PSR3_WUA_MASK                    (0x20U)
1070 #define FLEXRAY_PSR3_WUA_SHIFT                   (5U)
1071 #define FLEXRAY_PSR3_WUA_WIDTH                   (1U)
1072 #define FLEXRAY_PSR3_WUA(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_WUA_SHIFT)) & FLEXRAY_PSR3_WUA_MASK)
1073 
1074 #define FLEXRAY_PSR3_AVFB_MASK                   (0x100U)
1075 #define FLEXRAY_PSR3_AVFB_SHIFT                  (8U)
1076 #define FLEXRAY_PSR3_AVFB_WIDTH                  (1U)
1077 #define FLEXRAY_PSR3_AVFB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_AVFB_SHIFT)) & FLEXRAY_PSR3_AVFB_MASK)
1078 
1079 #define FLEXRAY_PSR3_ASEB_MASK                   (0x200U)
1080 #define FLEXRAY_PSR3_ASEB_SHIFT                  (9U)
1081 #define FLEXRAY_PSR3_ASEB_WIDTH                  (1U)
1082 #define FLEXRAY_PSR3_ASEB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ASEB_SHIFT)) & FLEXRAY_PSR3_ASEB_MASK)
1083 
1084 #define FLEXRAY_PSR3_ACEB_MASK                   (0x400U)
1085 #define FLEXRAY_PSR3_ACEB_SHIFT                  (10U)
1086 #define FLEXRAY_PSR3_ACEB_WIDTH                  (1U)
1087 #define FLEXRAY_PSR3_ACEB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ACEB_SHIFT)) & FLEXRAY_PSR3_ACEB_MASK)
1088 
1089 #define FLEXRAY_PSR3_AACB_MASK                   (0x800U)
1090 #define FLEXRAY_PSR3_AACB_SHIFT                  (11U)
1091 #define FLEXRAY_PSR3_AACB_WIDTH                  (1U)
1092 #define FLEXRAY_PSR3_AACB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_AACB_SHIFT)) & FLEXRAY_PSR3_AACB_MASK)
1093 
1094 #define FLEXRAY_PSR3_ABVB_MASK                   (0x1000U)
1095 #define FLEXRAY_PSR3_ABVB_SHIFT                  (12U)
1096 #define FLEXRAY_PSR3_ABVB_WIDTH                  (1U)
1097 #define FLEXRAY_PSR3_ABVB(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_ABVB_SHIFT)) & FLEXRAY_PSR3_ABVB_MASK)
1098 
1099 #define FLEXRAY_PSR3_WUB_MASK                    (0x2000U)
1100 #define FLEXRAY_PSR3_WUB_SHIFT                   (13U)
1101 #define FLEXRAY_PSR3_WUB_WIDTH                   (1U)
1102 #define FLEXRAY_PSR3_WUB(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PSR3_WUB_SHIFT)) & FLEXRAY_PSR3_WUB_MASK)
1103 /*! @} */
1104 
1105 /*! @name MTCTR - MT Counter */
1106 /*! @{ */
1107 
1108 #define FLEXRAY_MTCTR_MTCT_MASK                  (0x3FFFU)
1109 #define FLEXRAY_MTCTR_MTCT_SHIFT                 (0U)
1110 #define FLEXRAY_MTCTR_MTCT_WIDTH                 (14U)
1111 #define FLEXRAY_MTCTR_MTCT(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTCTR_MTCT_SHIFT)) & FLEXRAY_MTCTR_MTCT_MASK)
1112 /*! @} */
1113 
1114 /*! @name CYCTR - Cycle Counter */
1115 /*! @{ */
1116 
1117 #define FLEXRAY_CYCTR_CYCCNT_MASK                (0x3FU)
1118 #define FLEXRAY_CYCTR_CYCCNT_SHIFT               (0U)
1119 #define FLEXRAY_CYCTR_CYCCNT_WIDTH               (6U)
1120 #define FLEXRAY_CYCTR_CYCCNT(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CYCTR_CYCCNT_SHIFT)) & FLEXRAY_CYCTR_CYCCNT_MASK)
1121 /*! @} */
1122 
1123 /*! @name SLTCTAR - Slot Counter Channel A */
1124 /*! @{ */
1125 
1126 #define FLEXRAY_SLTCTAR_SLOTCNTA_MASK            (0x7FFU)
1127 #define FLEXRAY_SLTCTAR_SLOTCNTA_SHIFT           (0U)
1128 #define FLEXRAY_SLTCTAR_SLOTCNTA_WIDTH           (11U)
1129 #define FLEXRAY_SLTCTAR_SLOTCNTA(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SLTCTAR_SLOTCNTA_SHIFT)) & FLEXRAY_SLTCTAR_SLOTCNTA_MASK)
1130 /*! @} */
1131 
1132 /*! @name SLTCTBR - Slot Counter Channel B */
1133 /*! @{ */
1134 
1135 #define FLEXRAY_SLTCTBR_SLOTCNTB_MASK            (0x7FFU)
1136 #define FLEXRAY_SLTCTBR_SLOTCNTB_SHIFT           (0U)
1137 #define FLEXRAY_SLTCTBR_SLOTCNTB_WIDTH           (11U)
1138 #define FLEXRAY_SLTCTBR_SLOTCNTB(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SLTCTBR_SLOTCNTB_SHIFT)) & FLEXRAY_SLTCTBR_SLOTCNTB_MASK)
1139 /*! @} */
1140 
1141 /*! @name RTCORVR - Rate Correction Value */
1142 /*! @{ */
1143 
1144 #define FLEXRAY_RTCORVR_RATECORR_MASK            (0xFFFFU)
1145 #define FLEXRAY_RTCORVR_RATECORR_SHIFT           (0U)
1146 #define FLEXRAY_RTCORVR_RATECORR_WIDTH           (16U)
1147 #define FLEXRAY_RTCORVR_RATECORR(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RTCORVR_RATECORR_SHIFT)) & FLEXRAY_RTCORVR_RATECORR_MASK)
1148 /*! @} */
1149 
1150 /*! @name OFCORVR - Offset Correction Value */
1151 /*! @{ */
1152 
1153 #define FLEXRAY_OFCORVR_OFFSETCORR_MASK          (0xFFFFU)
1154 #define FLEXRAY_OFCORVR_OFFSETCORR_SHIFT         (0U)
1155 #define FLEXRAY_OFCORVR_OFFSETCORR_WIDTH         (16U)
1156 #define FLEXRAY_OFCORVR_OFFSETCORR(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_OFCORVR_OFFSETCORR_SHIFT)) & FLEXRAY_OFCORVR_OFFSETCORR_MASK)
1157 /*! @} */
1158 
1159 /*! @name CIFR - Combined Interrupt Flag */
1160 /*! @{ */
1161 
1162 #define FLEXRAY_CIFR_TBIF_MASK                   (0x1U)
1163 #define FLEXRAY_CIFR_TBIF_SHIFT                  (0U)
1164 #define FLEXRAY_CIFR_TBIF_WIDTH                  (1U)
1165 #define FLEXRAY_CIFR_TBIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_TBIF_SHIFT)) & FLEXRAY_CIFR_TBIF_MASK)
1166 
1167 #define FLEXRAY_CIFR_RBIF_MASK                   (0x2U)
1168 #define FLEXRAY_CIFR_RBIF_SHIFT                  (1U)
1169 #define FLEXRAY_CIFR_RBIF_WIDTH                  (1U)
1170 #define FLEXRAY_CIFR_RBIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_RBIF_SHIFT)) & FLEXRAY_CIFR_RBIF_MASK)
1171 
1172 #define FLEXRAY_CIFR_FAFAIF_MASK                 (0x4U)
1173 #define FLEXRAY_CIFR_FAFAIF_SHIFT                (2U)
1174 #define FLEXRAY_CIFR_FAFAIF_WIDTH                (1U)
1175 #define FLEXRAY_CIFR_FAFAIF(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_FAFAIF_SHIFT)) & FLEXRAY_CIFR_FAFAIF_MASK)
1176 
1177 #define FLEXRAY_CIFR_FAFBIF_MASK                 (0x8U)
1178 #define FLEXRAY_CIFR_FAFBIF_SHIFT                (3U)
1179 #define FLEXRAY_CIFR_FAFBIF_WIDTH                (1U)
1180 #define FLEXRAY_CIFR_FAFBIF(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_FAFBIF_SHIFT)) & FLEXRAY_CIFR_FAFBIF_MASK)
1181 
1182 #define FLEXRAY_CIFR_WUPIF_MASK                  (0x10U)
1183 #define FLEXRAY_CIFR_WUPIF_SHIFT                 (4U)
1184 #define FLEXRAY_CIFR_WUPIF_WIDTH                 (1U)
1185 #define FLEXRAY_CIFR_WUPIF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_WUPIF_SHIFT)) & FLEXRAY_CIFR_WUPIF_MASK)
1186 
1187 #define FLEXRAY_CIFR_CHIF_MASK                   (0x20U)
1188 #define FLEXRAY_CIFR_CHIF_SHIFT                  (5U)
1189 #define FLEXRAY_CIFR_CHIF_WIDTH                  (1U)
1190 #define FLEXRAY_CIFR_CHIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_CHIF_SHIFT)) & FLEXRAY_CIFR_CHIF_MASK)
1191 
1192 #define FLEXRAY_CIFR_PRIF_MASK                   (0x40U)
1193 #define FLEXRAY_CIFR_PRIF_SHIFT                  (6U)
1194 #define FLEXRAY_CIFR_PRIF_WIDTH                  (1U)
1195 #define FLEXRAY_CIFR_PRIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_PRIF_SHIFT)) & FLEXRAY_CIFR_PRIF_MASK)
1196 
1197 #define FLEXRAY_CIFR_MIF_MASK                    (0x80U)
1198 #define FLEXRAY_CIFR_MIF_SHIFT                   (7U)
1199 #define FLEXRAY_CIFR_MIF_WIDTH                   (1U)
1200 #define FLEXRAY_CIFR_MIF(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CIFR_MIF_SHIFT)) & FLEXRAY_CIFR_MIF_MASK)
1201 /*! @} */
1202 
1203 /*! @name SYMATOR - System Memory Access Timeout */
1204 /*! @{ */
1205 
1206 #define FLEXRAY_SYMATOR_TIMEOUT_MASK             (0xFFU)
1207 #define FLEXRAY_SYMATOR_TIMEOUT_SHIFT            (0U)
1208 #define FLEXRAY_SYMATOR_TIMEOUT_WIDTH            (8U)
1209 #define FLEXRAY_SYMATOR_TIMEOUT(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SYMATOR_TIMEOUT_SHIFT)) & FLEXRAY_SYMATOR_TIMEOUT_MASK)
1210 /*! @} */
1211 
1212 /*! @name SFCNTR - Sync Frame Counter */
1213 /*! @{ */
1214 
1215 #define FLEXRAY_SFCNTR_SFODA_MASK                (0xFU)
1216 #define FLEXRAY_SFCNTR_SFODA_SHIFT               (0U)
1217 #define FLEXRAY_SFCNTR_SFODA_WIDTH               (4U)
1218 #define FLEXRAY_SFCNTR_SFODA(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFCNTR_SFODA_SHIFT)) & FLEXRAY_SFCNTR_SFODA_MASK)
1219 
1220 #define FLEXRAY_SFCNTR_SFODB_MASK                (0xF0U)
1221 #define FLEXRAY_SFCNTR_SFODB_SHIFT               (4U)
1222 #define FLEXRAY_SFCNTR_SFODB_WIDTH               (4U)
1223 #define FLEXRAY_SFCNTR_SFODB(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFCNTR_SFODB_SHIFT)) & FLEXRAY_SFCNTR_SFODB_MASK)
1224 
1225 #define FLEXRAY_SFCNTR_SFEVA_MASK                (0xF00U)
1226 #define FLEXRAY_SFCNTR_SFEVA_SHIFT               (8U)
1227 #define FLEXRAY_SFCNTR_SFEVA_WIDTH               (4U)
1228 #define FLEXRAY_SFCNTR_SFEVA(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFCNTR_SFEVA_SHIFT)) & FLEXRAY_SFCNTR_SFEVA_MASK)
1229 
1230 #define FLEXRAY_SFCNTR_SFEVB_MASK                (0xF000U)
1231 #define FLEXRAY_SFCNTR_SFEVB_SHIFT               (12U)
1232 #define FLEXRAY_SFCNTR_SFEVB_WIDTH               (4U)
1233 #define FLEXRAY_SFCNTR_SFEVB(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFCNTR_SFEVB_SHIFT)) & FLEXRAY_SFCNTR_SFEVB_MASK)
1234 /*! @} */
1235 
1236 /*! @name SFTOR - Sync Frame Table Offset */
1237 /*! @{ */
1238 
1239 #define FLEXRAY_SFTOR_SFT_OFFSET_MASK            (0xFFFEU)
1240 #define FLEXRAY_SFTOR_SFT_OFFSET_SHIFT           (1U)
1241 #define FLEXRAY_SFTOR_SFT_OFFSET_WIDTH           (15U)
1242 #define FLEXRAY_SFTOR_SFT_OFFSET(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTOR_SFT_OFFSET_SHIFT)) & FLEXRAY_SFTOR_SFT_OFFSET_MASK)
1243 /*! @} */
1244 
1245 /*! @name SFTCCSR - Sync Frame Table Configuration Control Status */
1246 /*! @{ */
1247 
1248 #define FLEXRAY_SFTCCSR_SIDEN_MASK               (0x1U)
1249 #define FLEXRAY_SFTCCSR_SIDEN_SHIFT              (0U)
1250 #define FLEXRAY_SFTCCSR_SIDEN_WIDTH              (1U)
1251 #define FLEXRAY_SFTCCSR_SIDEN(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_SIDEN_SHIFT)) & FLEXRAY_SFTCCSR_SIDEN_MASK)
1252 
1253 #define FLEXRAY_SFTCCSR_SDVEN_MASK               (0x2U)
1254 #define FLEXRAY_SFTCCSR_SDVEN_SHIFT              (1U)
1255 #define FLEXRAY_SFTCCSR_SDVEN_WIDTH              (1U)
1256 #define FLEXRAY_SFTCCSR_SDVEN(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_SDVEN_SHIFT)) & FLEXRAY_SFTCCSR_SDVEN_MASK)
1257 
1258 #define FLEXRAY_SFTCCSR_OPT_MASK                 (0x4U)
1259 #define FLEXRAY_SFTCCSR_OPT_SHIFT                (2U)
1260 #define FLEXRAY_SFTCCSR_OPT_WIDTH                (1U)
1261 #define FLEXRAY_SFTCCSR_OPT(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_OPT_SHIFT)) & FLEXRAY_SFTCCSR_OPT_MASK)
1262 
1263 #define FLEXRAY_SFTCCSR_OVAL_MASK                (0x10U)
1264 #define FLEXRAY_SFTCCSR_OVAL_SHIFT               (4U)
1265 #define FLEXRAY_SFTCCSR_OVAL_WIDTH               (1U)
1266 #define FLEXRAY_SFTCCSR_OVAL(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_OVAL_SHIFT)) & FLEXRAY_SFTCCSR_OVAL_MASK)
1267 
1268 #define FLEXRAY_SFTCCSR_EVAL_MASK                (0x20U)
1269 #define FLEXRAY_SFTCCSR_EVAL_SHIFT               (5U)
1270 #define FLEXRAY_SFTCCSR_EVAL_WIDTH               (1U)
1271 #define FLEXRAY_SFTCCSR_EVAL(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_EVAL_SHIFT)) & FLEXRAY_SFTCCSR_EVAL_MASK)
1272 
1273 #define FLEXRAY_SFTCCSR_OLKS_MASK                (0x40U)
1274 #define FLEXRAY_SFTCCSR_OLKS_SHIFT               (6U)
1275 #define FLEXRAY_SFTCCSR_OLKS_WIDTH               (1U)
1276 #define FLEXRAY_SFTCCSR_OLKS(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_OLKS_SHIFT)) & FLEXRAY_SFTCCSR_OLKS_MASK)
1277 
1278 #define FLEXRAY_SFTCCSR_ELKS_MASK                (0x80U)
1279 #define FLEXRAY_SFTCCSR_ELKS_SHIFT               (7U)
1280 #define FLEXRAY_SFTCCSR_ELKS_WIDTH               (1U)
1281 #define FLEXRAY_SFTCCSR_ELKS(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_ELKS_SHIFT)) & FLEXRAY_SFTCCSR_ELKS_MASK)
1282 
1283 #define FLEXRAY_SFTCCSR_CYCNUM_MASK              (0x3F00U)
1284 #define FLEXRAY_SFTCCSR_CYCNUM_SHIFT             (8U)
1285 #define FLEXRAY_SFTCCSR_CYCNUM_WIDTH             (6U)
1286 #define FLEXRAY_SFTCCSR_CYCNUM(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_CYCNUM_SHIFT)) & FLEXRAY_SFTCCSR_CYCNUM_MASK)
1287 
1288 #define FLEXRAY_SFTCCSR_OLKT_MASK                (0x4000U)
1289 #define FLEXRAY_SFTCCSR_OLKT_SHIFT               (14U)
1290 #define FLEXRAY_SFTCCSR_OLKT_WIDTH               (1U)
1291 #define FLEXRAY_SFTCCSR_OLKT(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_OLKT_SHIFT)) & FLEXRAY_SFTCCSR_OLKT_MASK)
1292 
1293 #define FLEXRAY_SFTCCSR_ELKT_MASK                (0x8000U)
1294 #define FLEXRAY_SFTCCSR_ELKT_SHIFT               (15U)
1295 #define FLEXRAY_SFTCCSR_ELKT_WIDTH               (1U)
1296 #define FLEXRAY_SFTCCSR_ELKT(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFTCCSR_ELKT_SHIFT)) & FLEXRAY_SFTCCSR_ELKT_MASK)
1297 /*! @} */
1298 
1299 /*! @name SFIDRFR - Sync Frame ID Rejection Filter */
1300 /*! @{ */
1301 
1302 #define FLEXRAY_SFIDRFR_SYNFRID_MASK             (0x3FFU)
1303 #define FLEXRAY_SFIDRFR_SYNFRID_SHIFT            (0U)
1304 #define FLEXRAY_SFIDRFR_SYNFRID_WIDTH            (10U)
1305 #define FLEXRAY_SFIDRFR_SYNFRID(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFIDRFR_SYNFRID_SHIFT)) & FLEXRAY_SFIDRFR_SYNFRID_MASK)
1306 /*! @} */
1307 
1308 /*! @name SFIDAFVR - Sync Frame ID Acceptance Filter Value */
1309 /*! @{ */
1310 
1311 #define FLEXRAY_SFIDAFVR_FVAL_MASK               (0x3FFU)
1312 #define FLEXRAY_SFIDAFVR_FVAL_SHIFT              (0U)
1313 #define FLEXRAY_SFIDAFVR_FVAL_WIDTH              (10U)
1314 #define FLEXRAY_SFIDAFVR_FVAL(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFIDAFVR_FVAL_SHIFT)) & FLEXRAY_SFIDAFVR_FVAL_MASK)
1315 /*! @} */
1316 
1317 /*! @name SFIDAFMR - Sync Frame ID Acceptance Filter Mask */
1318 /*! @{ */
1319 
1320 #define FLEXRAY_SFIDAFMR_FMSK_MASK               (0x3FFU)
1321 #define FLEXRAY_SFIDAFMR_FMSK_SHIFT              (0U)
1322 #define FLEXRAY_SFIDAFMR_FMSK_WIDTH              (10U)
1323 #define FLEXRAY_SFIDAFMR_FMSK(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SFIDAFMR_FMSK_SHIFT)) & FLEXRAY_SFIDAFMR_FMSK_MASK)
1324 /*! @} */
1325 
1326 /*! @name NMVR - NMV 0..NMV 5 */
1327 /*! @{ */
1328 
1329 #define FLEXRAY_NMVR_NMVP_MASK                   (0xFFFFU)
1330 #define FLEXRAY_NMVR_NMVP_SHIFT                  (0U)
1331 #define FLEXRAY_NMVR_NMVP_WIDTH                  (16U)
1332 #define FLEXRAY_NMVR_NMVP(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_NMVR_NMVP_SHIFT)) & FLEXRAY_NMVR_NMVP_MASK)
1333 /*! @} */
1334 
1335 /*! @name NMVLR - Network Management Vector Length Register */
1336 /*! @{ */
1337 
1338 #define FLEXRAY_NMVLR_NMVL_MASK                  (0xFU)
1339 #define FLEXRAY_NMVLR_NMVL_SHIFT                 (0U)
1340 #define FLEXRAY_NMVLR_NMVL_WIDTH                 (4U)
1341 #define FLEXRAY_NMVLR_NMVL(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_NMVLR_NMVL_SHIFT)) & FLEXRAY_NMVLR_NMVL_MASK)
1342 /*! @} */
1343 
1344 /*! @name TICCR - Timer Configuration And Control */
1345 /*! @{ */
1346 
1347 #define FLEXRAY_TICCR_T1ST_MASK                  (0x1U)
1348 #define FLEXRAY_TICCR_T1ST_SHIFT                 (0U)
1349 #define FLEXRAY_TICCR_T1ST_WIDTH                 (1U)
1350 #define FLEXRAY_TICCR_T1ST(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T1ST_SHIFT)) & FLEXRAY_TICCR_T1ST_MASK)
1351 
1352 #define FLEXRAY_TICCR_T1TR_MASK                  (0x2U)
1353 #define FLEXRAY_TICCR_T1TR_SHIFT                 (1U)
1354 #define FLEXRAY_TICCR_T1TR_WIDTH                 (1U)
1355 #define FLEXRAY_TICCR_T1TR(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T1TR_SHIFT)) & FLEXRAY_TICCR_T1TR_MASK)
1356 
1357 #define FLEXRAY_TICCR_T1SP_MASK                  (0x4U)
1358 #define FLEXRAY_TICCR_T1SP_SHIFT                 (2U)
1359 #define FLEXRAY_TICCR_T1SP_WIDTH                 (1U)
1360 #define FLEXRAY_TICCR_T1SP(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T1SP_SHIFT)) & FLEXRAY_TICCR_T1SP_MASK)
1361 
1362 #define FLEXRAY_TICCR_T1_REP_MASK                (0x10U)
1363 #define FLEXRAY_TICCR_T1_REP_SHIFT               (4U)
1364 #define FLEXRAY_TICCR_T1_REP_WIDTH               (1U)
1365 #define FLEXRAY_TICCR_T1_REP(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T1_REP_SHIFT)) & FLEXRAY_TICCR_T1_REP_MASK)
1366 
1367 #define FLEXRAY_TICCR_T2ST_MASK                  (0x100U)
1368 #define FLEXRAY_TICCR_T2ST_SHIFT                 (8U)
1369 #define FLEXRAY_TICCR_T2ST_WIDTH                 (1U)
1370 #define FLEXRAY_TICCR_T2ST(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T2ST_SHIFT)) & FLEXRAY_TICCR_T2ST_MASK)
1371 
1372 #define FLEXRAY_TICCR_T2TR_MASK                  (0x200U)
1373 #define FLEXRAY_TICCR_T2TR_SHIFT                 (9U)
1374 #define FLEXRAY_TICCR_T2TR_WIDTH                 (1U)
1375 #define FLEXRAY_TICCR_T2TR(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T2TR_SHIFT)) & FLEXRAY_TICCR_T2TR_MASK)
1376 
1377 #define FLEXRAY_TICCR_T2SP_MASK                  (0x400U)
1378 #define FLEXRAY_TICCR_T2SP_SHIFT                 (10U)
1379 #define FLEXRAY_TICCR_T2SP_WIDTH                 (1U)
1380 #define FLEXRAY_TICCR_T2SP(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T2SP_SHIFT)) & FLEXRAY_TICCR_T2SP_MASK)
1381 
1382 #define FLEXRAY_TICCR_T2_REP_MASK                (0x1000U)
1383 #define FLEXRAY_TICCR_T2_REP_SHIFT               (12U)
1384 #define FLEXRAY_TICCR_T2_REP_WIDTH               (1U)
1385 #define FLEXRAY_TICCR_T2_REP(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T2_REP_SHIFT)) & FLEXRAY_TICCR_T2_REP_MASK)
1386 
1387 #define FLEXRAY_TICCR_T2_CFG_MASK                (0x2000U)
1388 #define FLEXRAY_TICCR_T2_CFG_SHIFT               (13U)
1389 #define FLEXRAY_TICCR_T2_CFG_WIDTH               (1U)
1390 #define FLEXRAY_TICCR_T2_CFG(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TICCR_T2_CFG_SHIFT)) & FLEXRAY_TICCR_T2_CFG_MASK)
1391 /*! @} */
1392 
1393 /*! @name TI1CYSR - Timer 1 Cycle Set */
1394 /*! @{ */
1395 
1396 #define FLEXRAY_TI1CYSR_T1_CYC_MSK_MASK          (0x3FU)
1397 #define FLEXRAY_TI1CYSR_T1_CYC_MSK_SHIFT         (0U)
1398 #define FLEXRAY_TI1CYSR_T1_CYC_MSK_WIDTH         (6U)
1399 #define FLEXRAY_TI1CYSR_T1_CYC_MSK(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TI1CYSR_T1_CYC_MSK_SHIFT)) & FLEXRAY_TI1CYSR_T1_CYC_MSK_MASK)
1400 
1401 #define FLEXRAY_TI1CYSR_T1_CYC_VAL_MASK          (0x3F00U)
1402 #define FLEXRAY_TI1CYSR_T1_CYC_VAL_SHIFT         (8U)
1403 #define FLEXRAY_TI1CYSR_T1_CYC_VAL_WIDTH         (6U)
1404 #define FLEXRAY_TI1CYSR_T1_CYC_VAL(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TI1CYSR_T1_CYC_VAL_SHIFT)) & FLEXRAY_TI1CYSR_T1_CYC_VAL_MASK)
1405 /*! @} */
1406 
1407 /*! @name TI1MTOR - Timer 1 MT Offset */
1408 /*! @{ */
1409 
1410 #define FLEXRAY_TI1MTOR_T1_MTOFFSET_MASK         (0x3FFFU)
1411 #define FLEXRAY_TI1MTOR_T1_MTOFFSET_SHIFT        (0U)
1412 #define FLEXRAY_TI1MTOR_T1_MTOFFSET_WIDTH        (14U)
1413 #define FLEXRAY_TI1MTOR_T1_MTOFFSET(x)           (((uint16_t)(((uint16_t)(x)) << FLEXRAY_TI1MTOR_T1_MTOFFSET_SHIFT)) & FLEXRAY_TI1MTOR_T1_MTOFFSET_MASK)
1414 /*! @} */
1415 
1416 /*! @name ABS - Timer 2 Configuration 0 (Absolute Timer Configuration) */
1417 /*! @{ */
1418 
1419 #define FLEXRAY_ABS_T2CYCMSK_MASK                (0x3FU)
1420 #define FLEXRAY_ABS_T2CYCMSK_SHIFT               (0U)
1421 #define FLEXRAY_ABS_T2CYCMSK_WIDTH               (6U)
1422 #define FLEXRAY_ABS_T2CYCMSK(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_ABS_T2CYCMSK_SHIFT)) & FLEXRAY_ABS_T2CYCMSK_MASK)
1423 
1424 #define FLEXRAY_ABS_T2CYCVAL_MASK                (0x3F00U)
1425 #define FLEXRAY_ABS_T2CYCVAL_SHIFT               (8U)
1426 #define FLEXRAY_ABS_T2CYCVAL_WIDTH               (6U)
1427 #define FLEXRAY_ABS_T2CYCVAL(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_ABS_T2CYCVAL_SHIFT)) & FLEXRAY_ABS_T2CYCVAL_MASK)
1428 /*! @} */
1429 
1430 /*! @name REL - Timer 2 Configuration 0 (Relative Timer Configuration) */
1431 /*! @{ */
1432 
1433 #define FLEXRAY_REL_T2MTCNT_MASK                 (0xFFFFU)
1434 #define FLEXRAY_REL_T2MTCNT_SHIFT                (0U)
1435 #define FLEXRAY_REL_T2MTCNT_WIDTH                (16U)
1436 #define FLEXRAY_REL_T2MTCNT(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_REL_T2MTCNT_SHIFT)) & FLEXRAY_REL_T2MTCNT_MASK)
1437 /*! @} */
1438 
1439 /*! @name ABS - Timer 2 Configuration 1 (Absolute Timer Configuration) */
1440 /*! @{ */
1441 
1442 #define FLEXRAY_ABS_T2MOFF_MASK                  (0x3FFFU)
1443 #define FLEXRAY_ABS_T2MOFF_SHIFT                 (0U)
1444 #define FLEXRAY_ABS_T2MOFF_WIDTH                 (14U)
1445 #define FLEXRAY_ABS_T2MOFF(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_ABS_T2MOFF_SHIFT)) & FLEXRAY_ABS_T2MOFF_MASK)
1446 /*! @} */
1447 
1448 /*! @name REL - Timer 2 Configuration 1 (Relative Timer Configuration) */
1449 /*! @{ */
1450 
1451 #define FLEXRAY_REL_T2MTCNT_MASK                 (0xFFFFU)
1452 #define FLEXRAY_REL_T2MTCNT_SHIFT                (0U)
1453 #define FLEXRAY_REL_T2MTCNT_WIDTH                (16U)
1454 #define FLEXRAY_REL_T2MTCNT(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_REL_T2MTCNT_SHIFT)) & FLEXRAY_REL_T2MTCNT_MASK)
1455 /*! @} */
1456 
1457 /*! @name SSSR - Slot Status Selection */
1458 /*! @{ */
1459 
1460 #define FLEXRAY_SSSR_SLOTNUMBER_MASK             (0x7FFU)
1461 #define FLEXRAY_SSSR_SLOTNUMBER_SHIFT            (0U)
1462 #define FLEXRAY_SSSR_SLOTNUMBER_WIDTH            (11U)
1463 #define FLEXRAY_SSSR_SLOTNUMBER(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSSR_SLOTNUMBER_SHIFT)) & FLEXRAY_SSSR_SLOTNUMBER_MASK)
1464 
1465 #define FLEXRAY_SSSR_SEL_MASK                    (0x3000U)
1466 #define FLEXRAY_SSSR_SEL_SHIFT                   (12U)
1467 #define FLEXRAY_SSSR_SEL_WIDTH                   (2U)
1468 #define FLEXRAY_SSSR_SEL(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSSR_SEL_SHIFT)) & FLEXRAY_SSSR_SEL_MASK)
1469 
1470 #define FLEXRAY_SSSR_WMD_MASK                    (0x8000U)
1471 #define FLEXRAY_SSSR_WMD_SHIFT                   (15U)
1472 #define FLEXRAY_SSSR_WMD_WIDTH                   (1U)
1473 #define FLEXRAY_SSSR_WMD(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSSR_WMD_SHIFT)) & FLEXRAY_SSSR_WMD_MASK)
1474 /*! @} */
1475 
1476 /*! @name SSCCR - Slot Status Counter Condition */
1477 /*! @{ */
1478 
1479 #define FLEXRAY_SSCCR_STATUSMASK_MASK            (0xFU)
1480 #define FLEXRAY_SSCCR_STATUSMASK_SHIFT           (0U)
1481 #define FLEXRAY_SSCCR_STATUSMASK_WIDTH           (4U)
1482 #define FLEXRAY_SSCCR_STATUSMASK(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_STATUSMASK_SHIFT)) & FLEXRAY_SSCCR_STATUSMASK_MASK)
1483 
1484 #define FLEXRAY_SSCCR_SUF_MASK                   (0x10U)
1485 #define FLEXRAY_SSCCR_SUF_SHIFT                  (4U)
1486 #define FLEXRAY_SSCCR_SUF_WIDTH                  (1U)
1487 #define FLEXRAY_SSCCR_SUF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_SUF_SHIFT)) & FLEXRAY_SSCCR_SUF_MASK)
1488 
1489 #define FLEXRAY_SSCCR_NUF_MASK                   (0x20U)
1490 #define FLEXRAY_SSCCR_NUF_SHIFT                  (5U)
1491 #define FLEXRAY_SSCCR_NUF_WIDTH                  (1U)
1492 #define FLEXRAY_SSCCR_NUF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_NUF_SHIFT)) & FLEXRAY_SSCCR_NUF_MASK)
1493 
1494 #define FLEXRAY_SSCCR_SYF_MASK                   (0x40U)
1495 #define FLEXRAY_SSCCR_SYF_SHIFT                  (6U)
1496 #define FLEXRAY_SSCCR_SYF_WIDTH                  (1U)
1497 #define FLEXRAY_SSCCR_SYF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_SYF_SHIFT)) & FLEXRAY_SSCCR_SYF_MASK)
1498 
1499 #define FLEXRAY_SSCCR_VFR_MASK                   (0x80U)
1500 #define FLEXRAY_SSCCR_VFR_SHIFT                  (7U)
1501 #define FLEXRAY_SSCCR_VFR_WIDTH                  (1U)
1502 #define FLEXRAY_SSCCR_VFR(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_VFR_SHIFT)) & FLEXRAY_SSCCR_VFR_MASK)
1503 
1504 #define FLEXRAY_SSCCR_MCY_MASK                   (0x100U)
1505 #define FLEXRAY_SSCCR_MCY_SHIFT                  (8U)
1506 #define FLEXRAY_SSCCR_MCY_WIDTH                  (1U)
1507 #define FLEXRAY_SSCCR_MCY(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_MCY_SHIFT)) & FLEXRAY_SSCCR_MCY_MASK)
1508 
1509 #define FLEXRAY_SSCCR_CNTCFG_MASK                (0x600U)
1510 #define FLEXRAY_SSCCR_CNTCFG_SHIFT               (9U)
1511 #define FLEXRAY_SSCCR_CNTCFG_WIDTH               (2U)
1512 #define FLEXRAY_SSCCR_CNTCFG(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_CNTCFG_SHIFT)) & FLEXRAY_SSCCR_CNTCFG_MASK)
1513 
1514 #define FLEXRAY_SSCCR_SEL_MASK                   (0x3000U)
1515 #define FLEXRAY_SSCCR_SEL_SHIFT                  (12U)
1516 #define FLEXRAY_SSCCR_SEL_WIDTH                  (2U)
1517 #define FLEXRAY_SSCCR_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_SEL_SHIFT)) & FLEXRAY_SSCCR_SEL_MASK)
1518 
1519 #define FLEXRAY_SSCCR_WMD_MASK                   (0x8000U)
1520 #define FLEXRAY_SSCCR_WMD_SHIFT                  (15U)
1521 #define FLEXRAY_SSCCR_WMD_WIDTH                  (1U)
1522 #define FLEXRAY_SSCCR_WMD(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCCR_WMD_SHIFT)) & FLEXRAY_SSCCR_WMD_MASK)
1523 /*! @} */
1524 
1525 /*! @name SSR - Slot Status */
1526 /*! @{ */
1527 
1528 #define FLEXRAY_SSR_TCA_MASK                     (0x1U)
1529 #define FLEXRAY_SSR_TCA_SHIFT                    (0U)
1530 #define FLEXRAY_SSR_TCA_WIDTH                    (1U)
1531 #define FLEXRAY_SSR_TCA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_TCA_SHIFT)) & FLEXRAY_SSR_TCA_MASK)
1532 
1533 #define FLEXRAY_SSR_BVA_MASK                     (0x2U)
1534 #define FLEXRAY_SSR_BVA_SHIFT                    (1U)
1535 #define FLEXRAY_SSR_BVA_WIDTH                    (1U)
1536 #define FLEXRAY_SSR_BVA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_BVA_SHIFT)) & FLEXRAY_SSR_BVA_MASK)
1537 
1538 #define FLEXRAY_SSR_CEA_MASK                     (0x4U)
1539 #define FLEXRAY_SSR_CEA_SHIFT                    (2U)
1540 #define FLEXRAY_SSR_CEA_WIDTH                    (1U)
1541 #define FLEXRAY_SSR_CEA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_CEA_SHIFT)) & FLEXRAY_SSR_CEA_MASK)
1542 
1543 #define FLEXRAY_SSR_SEA_MASK                     (0x8U)
1544 #define FLEXRAY_SSR_SEA_SHIFT                    (3U)
1545 #define FLEXRAY_SSR_SEA_WIDTH                    (1U)
1546 #define FLEXRAY_SSR_SEA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SEA_SHIFT)) & FLEXRAY_SSR_SEA_MASK)
1547 
1548 #define FLEXRAY_SSR_SUA_MASK                     (0x10U)
1549 #define FLEXRAY_SSR_SUA_SHIFT                    (4U)
1550 #define FLEXRAY_SSR_SUA_WIDTH                    (1U)
1551 #define FLEXRAY_SSR_SUA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SUA_SHIFT)) & FLEXRAY_SSR_SUA_MASK)
1552 
1553 #define FLEXRAY_SSR_NFA_MASK                     (0x20U)
1554 #define FLEXRAY_SSR_NFA_SHIFT                    (5U)
1555 #define FLEXRAY_SSR_NFA_WIDTH                    (1U)
1556 #define FLEXRAY_SSR_NFA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_NFA_SHIFT)) & FLEXRAY_SSR_NFA_MASK)
1557 
1558 #define FLEXRAY_SSR_SYA_MASK                     (0x40U)
1559 #define FLEXRAY_SSR_SYA_SHIFT                    (6U)
1560 #define FLEXRAY_SSR_SYA_WIDTH                    (1U)
1561 #define FLEXRAY_SSR_SYA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SYA_SHIFT)) & FLEXRAY_SSR_SYA_MASK)
1562 
1563 #define FLEXRAY_SSR_VFA_MASK                     (0x80U)
1564 #define FLEXRAY_SSR_VFA_SHIFT                    (7U)
1565 #define FLEXRAY_SSR_VFA_WIDTH                    (1U)
1566 #define FLEXRAY_SSR_VFA(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_VFA_SHIFT)) & FLEXRAY_SSR_VFA_MASK)
1567 
1568 #define FLEXRAY_SSR_TCB_MASK                     (0x100U)
1569 #define FLEXRAY_SSR_TCB_SHIFT                    (8U)
1570 #define FLEXRAY_SSR_TCB_WIDTH                    (1U)
1571 #define FLEXRAY_SSR_TCB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_TCB_SHIFT)) & FLEXRAY_SSR_TCB_MASK)
1572 
1573 #define FLEXRAY_SSR_BVB_MASK                     (0x200U)
1574 #define FLEXRAY_SSR_BVB_SHIFT                    (9U)
1575 #define FLEXRAY_SSR_BVB_WIDTH                    (1U)
1576 #define FLEXRAY_SSR_BVB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_BVB_SHIFT)) & FLEXRAY_SSR_BVB_MASK)
1577 
1578 #define FLEXRAY_SSR_CEB_MASK                     (0x400U)
1579 #define FLEXRAY_SSR_CEB_SHIFT                    (10U)
1580 #define FLEXRAY_SSR_CEB_WIDTH                    (1U)
1581 #define FLEXRAY_SSR_CEB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_CEB_SHIFT)) & FLEXRAY_SSR_CEB_MASK)
1582 
1583 #define FLEXRAY_SSR_SEB_MASK                     (0x800U)
1584 #define FLEXRAY_SSR_SEB_SHIFT                    (11U)
1585 #define FLEXRAY_SSR_SEB_WIDTH                    (1U)
1586 #define FLEXRAY_SSR_SEB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SEB_SHIFT)) & FLEXRAY_SSR_SEB_MASK)
1587 
1588 #define FLEXRAY_SSR_SUB_MASK                     (0x1000U)
1589 #define FLEXRAY_SSR_SUB_SHIFT                    (12U)
1590 #define FLEXRAY_SSR_SUB_WIDTH                    (1U)
1591 #define FLEXRAY_SSR_SUB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SUB_SHIFT)) & FLEXRAY_SSR_SUB_MASK)
1592 
1593 #define FLEXRAY_SSR_NFB_MASK                     (0x2000U)
1594 #define FLEXRAY_SSR_NFB_SHIFT                    (13U)
1595 #define FLEXRAY_SSR_NFB_WIDTH                    (1U)
1596 #define FLEXRAY_SSR_NFB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_NFB_SHIFT)) & FLEXRAY_SSR_NFB_MASK)
1597 
1598 #define FLEXRAY_SSR_SYB_MASK                     (0x4000U)
1599 #define FLEXRAY_SSR_SYB_SHIFT                    (14U)
1600 #define FLEXRAY_SSR_SYB_WIDTH                    (1U)
1601 #define FLEXRAY_SSR_SYB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_SYB_SHIFT)) & FLEXRAY_SSR_SYB_MASK)
1602 
1603 #define FLEXRAY_SSR_VFB_MASK                     (0x8000U)
1604 #define FLEXRAY_SSR_VFB_SHIFT                    (15U)
1605 #define FLEXRAY_SSR_VFB_WIDTH                    (1U)
1606 #define FLEXRAY_SSR_VFB(x)                       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSR_VFB_SHIFT)) & FLEXRAY_SSR_VFB_MASK)
1607 /*! @} */
1608 
1609 /*! @name SSCR - Slot Status Counter */
1610 /*! @{ */
1611 
1612 #define FLEXRAY_SSCR_SLOTSTATUSCNT_MASK          (0xFFFFU)
1613 #define FLEXRAY_SSCR_SLOTSTATUSCNT_SHIFT         (0U)
1614 #define FLEXRAY_SSCR_SLOTSTATUSCNT_WIDTH         (16U)
1615 #define FLEXRAY_SSCR_SLOTSTATUSCNT(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_SSCR_SLOTSTATUSCNT_SHIFT)) & FLEXRAY_SSCR_SLOTSTATUSCNT_MASK)
1616 /*! @} */
1617 
1618 /*! @name MTSACFR - MTS A Configuration */
1619 /*! @{ */
1620 
1621 #define FLEXRAY_MTSACFR_CYCCNTVAL_MASK           (0x3FU)
1622 #define FLEXRAY_MTSACFR_CYCCNTVAL_SHIFT          (0U)
1623 #define FLEXRAY_MTSACFR_CYCCNTVAL_WIDTH          (6U)
1624 #define FLEXRAY_MTSACFR_CYCCNTVAL(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSACFR_CYCCNTVAL_SHIFT)) & FLEXRAY_MTSACFR_CYCCNTVAL_MASK)
1625 
1626 #define FLEXRAY_MTSACFR_CYCCNTMSK_MASK           (0x3F00U)
1627 #define FLEXRAY_MTSACFR_CYCCNTMSK_SHIFT          (8U)
1628 #define FLEXRAY_MTSACFR_CYCCNTMSK_WIDTH          (6U)
1629 #define FLEXRAY_MTSACFR_CYCCNTMSK(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSACFR_CYCCNTMSK_SHIFT)) & FLEXRAY_MTSACFR_CYCCNTMSK_MASK)
1630 
1631 #define FLEXRAY_MTSACFR_MTE_MASK                 (0x8000U)
1632 #define FLEXRAY_MTSACFR_MTE_SHIFT                (15U)
1633 #define FLEXRAY_MTSACFR_MTE_WIDTH                (1U)
1634 #define FLEXRAY_MTSACFR_MTE(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSACFR_MTE_SHIFT)) & FLEXRAY_MTSACFR_MTE_MASK)
1635 /*! @} */
1636 
1637 /*! @name MTSBCFR - MTS B Configuration */
1638 /*! @{ */
1639 
1640 #define FLEXRAY_MTSBCFR_CYCCNTVAL_MASK           (0x3FU)
1641 #define FLEXRAY_MTSBCFR_CYCCNTVAL_SHIFT          (0U)
1642 #define FLEXRAY_MTSBCFR_CYCCNTVAL_WIDTH          (6U)
1643 #define FLEXRAY_MTSBCFR_CYCCNTVAL(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSBCFR_CYCCNTVAL_SHIFT)) & FLEXRAY_MTSBCFR_CYCCNTVAL_MASK)
1644 
1645 #define FLEXRAY_MTSBCFR_CYCCNTMSK_MASK           (0x3F00U)
1646 #define FLEXRAY_MTSBCFR_CYCCNTMSK_SHIFT          (8U)
1647 #define FLEXRAY_MTSBCFR_CYCCNTMSK_WIDTH          (6U)
1648 #define FLEXRAY_MTSBCFR_CYCCNTMSK(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSBCFR_CYCCNTMSK_SHIFT)) & FLEXRAY_MTSBCFR_CYCCNTMSK_MASK)
1649 
1650 #define FLEXRAY_MTSBCFR_MTE_MASK                 (0x8000U)
1651 #define FLEXRAY_MTSBCFR_MTE_SHIFT                (15U)
1652 #define FLEXRAY_MTSBCFR_MTE_WIDTH                (1U)
1653 #define FLEXRAY_MTSBCFR_MTE(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MTSBCFR_MTE_SHIFT)) & FLEXRAY_MTSBCFR_MTE_MASK)
1654 /*! @} */
1655 
1656 /*! @name RSBIR - Receive Shadow Buffer Index */
1657 /*! @{ */
1658 
1659 #define FLEXRAY_RSBIR_RSBIDX_MASK                (0x1FFU)
1660 #define FLEXRAY_RSBIR_RSBIDX_SHIFT               (0U)
1661 #define FLEXRAY_RSBIR_RSBIDX_WIDTH               (9U)
1662 #define FLEXRAY_RSBIR_RSBIDX(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RSBIR_RSBIDX_SHIFT)) & FLEXRAY_RSBIR_RSBIDX_MASK)
1663 
1664 #define FLEXRAY_RSBIR_SEL_MASK                   (0x3000U)
1665 #define FLEXRAY_RSBIR_SEL_SHIFT                  (12U)
1666 #define FLEXRAY_RSBIR_SEL_WIDTH                  (2U)
1667 #define FLEXRAY_RSBIR_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RSBIR_SEL_SHIFT)) & FLEXRAY_RSBIR_SEL_MASK)
1668 
1669 #define FLEXRAY_RSBIR_WMD_MASK                   (0x8000U)
1670 #define FLEXRAY_RSBIR_WMD_SHIFT                  (15U)
1671 #define FLEXRAY_RSBIR_WMD_WIDTH                  (1U)
1672 #define FLEXRAY_RSBIR_WMD(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RSBIR_WMD_SHIFT)) & FLEXRAY_RSBIR_WMD_MASK)
1673 /*! @} */
1674 
1675 /*! @name RFWMSR - Receive FIFO Watermark And Selection */
1676 /*! @{ */
1677 
1678 #define FLEXRAY_RFWMSR_SEL_MASK                  (0x1U)
1679 #define FLEXRAY_RFWMSR_SEL_SHIFT                 (0U)
1680 #define FLEXRAY_RFWMSR_SEL_WIDTH                 (1U)
1681 #define FLEXRAY_RFWMSR_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFWMSR_SEL_SHIFT)) & FLEXRAY_RFWMSR_SEL_MASK)
1682 
1683 #define FLEXRAY_RFWMSR_WM_MASK                   (0xFF00U)
1684 #define FLEXRAY_RFWMSR_WM_SHIFT                  (8U)
1685 #define FLEXRAY_RFWMSR_WM_WIDTH                  (8U)
1686 #define FLEXRAY_RFWMSR_WM(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFWMSR_WM_SHIFT)) & FLEXRAY_RFWMSR_WM_MASK)
1687 /*! @} */
1688 
1689 /*! @name RFSIR - Receive FIFO Start Index */
1690 /*! @{ */
1691 
1692 #define FLEXRAY_RFSIR_SIDX_MASK                  (0x3FFU)
1693 #define FLEXRAY_RFSIR_SIDX_SHIFT                 (0U)
1694 #define FLEXRAY_RFSIR_SIDX_WIDTH                 (10U)
1695 #define FLEXRAY_RFSIR_SIDX(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFSIR_SIDX_SHIFT)) & FLEXRAY_RFSIR_SIDX_MASK)
1696 /*! @} */
1697 
1698 /*! @name RFDSR - Receive FIFO Depth And Size */
1699 /*! @{ */
1700 
1701 #define FLEXRAY_RFDSR_ENTRY_SIZE_MASK            (0x7FU)
1702 #define FLEXRAY_RFDSR_ENTRY_SIZE_SHIFT           (0U)
1703 #define FLEXRAY_RFDSR_ENTRY_SIZE_WIDTH           (7U)
1704 #define FLEXRAY_RFDSR_ENTRY_SIZE(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFDSR_ENTRY_SIZE_SHIFT)) & FLEXRAY_RFDSR_ENTRY_SIZE_MASK)
1705 
1706 #define FLEXRAY_RFDSR_FIFO_DEPTH_MASK            (0xFF00U)
1707 #define FLEXRAY_RFDSR_FIFO_DEPTH_SHIFT           (8U)
1708 #define FLEXRAY_RFDSR_FIFO_DEPTH_WIDTH           (8U)
1709 #define FLEXRAY_RFDSR_FIFO_DEPTH(x)              (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFDSR_FIFO_DEPTH_SHIFT)) & FLEXRAY_RFDSR_FIFO_DEPTH_MASK)
1710 /*! @} */
1711 
1712 /*! @name RFARIR - Receive FIFO A Read Index */
1713 /*! @{ */
1714 
1715 #define FLEXRAY_RFARIR_RDIDX_MASK                (0x3FFU)
1716 #define FLEXRAY_RFARIR_RDIDX_SHIFT               (0U)
1717 #define FLEXRAY_RFARIR_RDIDX_WIDTH               (10U)
1718 #define FLEXRAY_RFARIR_RDIDX(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFARIR_RDIDX_SHIFT)) & FLEXRAY_RFARIR_RDIDX_MASK)
1719 /*! @} */
1720 
1721 /*! @name RFBRIR - Receive FIFO B Read Index */
1722 /*! @{ */
1723 
1724 #define FLEXRAY_RFBRIR_RDIDX_MASK                (0x3FFU)
1725 #define FLEXRAY_RFBRIR_RDIDX_SHIFT               (0U)
1726 #define FLEXRAY_RFBRIR_RDIDX_WIDTH               (10U)
1727 #define FLEXRAY_RFBRIR_RDIDX(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFBRIR_RDIDX_SHIFT)) & FLEXRAY_RFBRIR_RDIDX_MASK)
1728 /*! @} */
1729 
1730 /*! @name RFMIDAFVR - Receive FIFO Message ID Acceptance Filter Value */
1731 /*! @{ */
1732 
1733 #define FLEXRAY_RFMIDAFVR_MIDAFVAL_MASK          (0xFFFFU)
1734 #define FLEXRAY_RFMIDAFVR_MIDAFVAL_SHIFT         (0U)
1735 #define FLEXRAY_RFMIDAFVR_MIDAFVAL_WIDTH         (16U)
1736 #define FLEXRAY_RFMIDAFVR_MIDAFVAL(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFMIDAFVR_MIDAFVAL_SHIFT)) & FLEXRAY_RFMIDAFVR_MIDAFVAL_MASK)
1737 /*! @} */
1738 
1739 /*! @name RFMIDAFMR - Receive FIFO Message ID Acceptance Filter Mask */
1740 /*! @{ */
1741 
1742 #define FLEXRAY_RFMIDAFMR_MIDAFMSK_MASK          (0xFFFFU)
1743 #define FLEXRAY_RFMIDAFMR_MIDAFMSK_SHIFT         (0U)
1744 #define FLEXRAY_RFMIDAFMR_MIDAFMSK_WIDTH         (16U)
1745 #define FLEXRAY_RFMIDAFMR_MIDAFMSK(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFMIDAFMR_MIDAFMSK_SHIFT)) & FLEXRAY_RFMIDAFMR_MIDAFMSK_MASK)
1746 /*! @} */
1747 
1748 /*! @name RFFIDRFVR - Receive FIFO Frame ID Rejection Filter Value */
1749 /*! @{ */
1750 
1751 #define FLEXRAY_RFFIDRFVR_FIDRFVAL_MASK          (0x7FFU)
1752 #define FLEXRAY_RFFIDRFVR_FIDRFVAL_SHIFT         (0U)
1753 #define FLEXRAY_RFFIDRFVR_FIDRFVAL_WIDTH         (11U)
1754 #define FLEXRAY_RFFIDRFVR_FIDRFVAL(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFFIDRFVR_FIDRFVAL_SHIFT)) & FLEXRAY_RFFIDRFVR_FIDRFVAL_MASK)
1755 /*! @} */
1756 
1757 /*! @name RFFIDRFMR - Receive FIFO Frame ID Rejection Filter Mask */
1758 /*! @{ */
1759 
1760 #define FLEXRAY_RFFIDRFMR_FIDRFMSK_MASK          (0x7FFU)
1761 #define FLEXRAY_RFFIDRFMR_FIDRFMSK_SHIFT         (0U)
1762 #define FLEXRAY_RFFIDRFMR_FIDRFMSK_WIDTH         (11U)
1763 #define FLEXRAY_RFFIDRFMR_FIDRFMSK(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFFIDRFMR_FIDRFMSK_SHIFT)) & FLEXRAY_RFFIDRFMR_FIDRFMSK_MASK)
1764 /*! @} */
1765 
1766 /*! @name RFRFCFR - Receive FIFO Range Filter Configuration */
1767 /*! @{ */
1768 
1769 #define FLEXRAY_RFRFCFR_SID_MASK                 (0x7FFU)
1770 #define FLEXRAY_RFRFCFR_SID_SHIFT                (0U)
1771 #define FLEXRAY_RFRFCFR_SID_WIDTH                (11U)
1772 #define FLEXRAY_RFRFCFR_SID(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCFR_SID_SHIFT)) & FLEXRAY_RFRFCFR_SID_MASK)
1773 
1774 #define FLEXRAY_RFRFCFR_SEL_MASK                 (0x3000U)
1775 #define FLEXRAY_RFRFCFR_SEL_SHIFT                (12U)
1776 #define FLEXRAY_RFRFCFR_SEL_WIDTH                (2U)
1777 #define FLEXRAY_RFRFCFR_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCFR_SEL_SHIFT)) & FLEXRAY_RFRFCFR_SEL_MASK)
1778 
1779 #define FLEXRAY_RFRFCFR_IBD_MASK                 (0x4000U)
1780 #define FLEXRAY_RFRFCFR_IBD_SHIFT                (14U)
1781 #define FLEXRAY_RFRFCFR_IBD_WIDTH                (1U)
1782 #define FLEXRAY_RFRFCFR_IBD(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCFR_IBD_SHIFT)) & FLEXRAY_RFRFCFR_IBD_MASK)
1783 
1784 #define FLEXRAY_RFRFCFR_WMD_MASK                 (0x8000U)
1785 #define FLEXRAY_RFRFCFR_WMD_SHIFT                (15U)
1786 #define FLEXRAY_RFRFCFR_WMD_WIDTH                (1U)
1787 #define FLEXRAY_RFRFCFR_WMD(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCFR_WMD_SHIFT)) & FLEXRAY_RFRFCFR_WMD_MASK)
1788 /*! @} */
1789 
1790 /*! @name RFRFCTR - Receive FIFO Range Filter Control */
1791 /*! @{ */
1792 
1793 #define FLEXRAY_RFRFCTR_F0EN_MASK                (0x1U)
1794 #define FLEXRAY_RFRFCTR_F0EN_SHIFT               (0U)
1795 #define FLEXRAY_RFRFCTR_F0EN_WIDTH               (1U)
1796 #define FLEXRAY_RFRFCTR_F0EN(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F0EN_SHIFT)) & FLEXRAY_RFRFCTR_F0EN_MASK)
1797 
1798 #define FLEXRAY_RFRFCTR_F1EN_MASK                (0x2U)
1799 #define FLEXRAY_RFRFCTR_F1EN_SHIFT               (1U)
1800 #define FLEXRAY_RFRFCTR_F1EN_WIDTH               (1U)
1801 #define FLEXRAY_RFRFCTR_F1EN(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F1EN_SHIFT)) & FLEXRAY_RFRFCTR_F1EN_MASK)
1802 
1803 #define FLEXRAY_RFRFCTR_F2EN_MASK                (0x4U)
1804 #define FLEXRAY_RFRFCTR_F2EN_SHIFT               (2U)
1805 #define FLEXRAY_RFRFCTR_F2EN_WIDTH               (1U)
1806 #define FLEXRAY_RFRFCTR_F2EN(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F2EN_SHIFT)) & FLEXRAY_RFRFCTR_F2EN_MASK)
1807 
1808 #define FLEXRAY_RFRFCTR_F3EN_MASK                (0x8U)
1809 #define FLEXRAY_RFRFCTR_F3EN_SHIFT               (3U)
1810 #define FLEXRAY_RFRFCTR_F3EN_WIDTH               (1U)
1811 #define FLEXRAY_RFRFCTR_F3EN(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F3EN_SHIFT)) & FLEXRAY_RFRFCTR_F3EN_MASK)
1812 
1813 #define FLEXRAY_RFRFCTR_F0MD_MASK                (0x100U)
1814 #define FLEXRAY_RFRFCTR_F0MD_SHIFT               (8U)
1815 #define FLEXRAY_RFRFCTR_F0MD_WIDTH               (1U)
1816 #define FLEXRAY_RFRFCTR_F0MD(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F0MD_SHIFT)) & FLEXRAY_RFRFCTR_F0MD_MASK)
1817 
1818 #define FLEXRAY_RFRFCTR_F1MD_MASK                (0x200U)
1819 #define FLEXRAY_RFRFCTR_F1MD_SHIFT               (9U)
1820 #define FLEXRAY_RFRFCTR_F1MD_WIDTH               (1U)
1821 #define FLEXRAY_RFRFCTR_F1MD(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F1MD_SHIFT)) & FLEXRAY_RFRFCTR_F1MD_MASK)
1822 
1823 #define FLEXRAY_RFRFCTR_F2MD_MASK                (0x400U)
1824 #define FLEXRAY_RFRFCTR_F2MD_SHIFT               (10U)
1825 #define FLEXRAY_RFRFCTR_F2MD_WIDTH               (1U)
1826 #define FLEXRAY_RFRFCTR_F2MD(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F2MD_SHIFT)) & FLEXRAY_RFRFCTR_F2MD_MASK)
1827 
1828 #define FLEXRAY_RFRFCTR_F3MD_MASK                (0x800U)
1829 #define FLEXRAY_RFRFCTR_F3MD_SHIFT               (11U)
1830 #define FLEXRAY_RFRFCTR_F3MD_WIDTH               (1U)
1831 #define FLEXRAY_RFRFCTR_F3MD(x)                  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFRFCTR_F3MD_SHIFT)) & FLEXRAY_RFRFCTR_F3MD_MASK)
1832 /*! @} */
1833 
1834 /*! @name LDTXSLAR - Last Dynamic Transmit Slot Channel A */
1835 /*! @{ */
1836 
1837 #define FLEXRAY_LDTXSLAR_LDYNTXSLOTA_MASK        (0x7FFU)
1838 #define FLEXRAY_LDTXSLAR_LDYNTXSLOTA_SHIFT       (0U)
1839 #define FLEXRAY_LDTXSLAR_LDYNTXSLOTA_WIDTH       (11U)
1840 #define FLEXRAY_LDTXSLAR_LDYNTXSLOTA(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_LDTXSLAR_LDYNTXSLOTA_SHIFT)) & FLEXRAY_LDTXSLAR_LDYNTXSLOTA_MASK)
1841 /*! @} */
1842 
1843 /*! @name LDTXSLBR - Last Dynamic Transmit Slot Channel B */
1844 /*! @{ */
1845 
1846 #define FLEXRAY_LDTXSLBR_LDYNTXSLOTB_MASK        (0x7FFU)
1847 #define FLEXRAY_LDTXSLBR_LDYNTXSLOTB_SHIFT       (0U)
1848 #define FLEXRAY_LDTXSLBR_LDYNTXSLOTB_WIDTH       (11U)
1849 #define FLEXRAY_LDTXSLBR_LDYNTXSLOTB(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_LDTXSLBR_LDYNTXSLOTB_SHIFT)) & FLEXRAY_LDTXSLBR_LDYNTXSLOTB_MASK)
1850 /*! @} */
1851 
1852 /*! @name PCR0 - Protocol Configuration 0 */
1853 /*! @{ */
1854 
1855 #define FLEXRAY_PCR0_static_slot_length_MASK     (0x3FFU)
1856 #define FLEXRAY_PCR0_static_slot_length_SHIFT    (0U)
1857 #define FLEXRAY_PCR0_static_slot_length_WIDTH    (10U)
1858 #define FLEXRAY_PCR0_static_slot_length(x)       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR0_static_slot_length_SHIFT)) & FLEXRAY_PCR0_static_slot_length_MASK)
1859 
1860 #define FLEXRAY_PCR0_action_point_offset_MASK    (0xFC00U)
1861 #define FLEXRAY_PCR0_action_point_offset_SHIFT   (10U)
1862 #define FLEXRAY_PCR0_action_point_offset_WIDTH   (6U)
1863 #define FLEXRAY_PCR0_action_point_offset(x)      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR0_action_point_offset_SHIFT)) & FLEXRAY_PCR0_action_point_offset_MASK)
1864 /*! @} */
1865 
1866 /*! @name PCR1 - Protocol Configuration 1 */
1867 /*! @{ */
1868 
1869 #define FLEXRAY_PCR1_macro_after_first_static_slot_MASK (0x3FFFU)
1870 #define FLEXRAY_PCR1_macro_after_first_static_slot_SHIFT (0U)
1871 #define FLEXRAY_PCR1_macro_after_first_static_slot_WIDTH (14U)
1872 #define FLEXRAY_PCR1_macro_after_first_static_slot(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR1_macro_after_first_static_slot_SHIFT)) & FLEXRAY_PCR1_macro_after_first_static_slot_MASK)
1873 /*! @} */
1874 
1875 /*! @name PCR2 - Protocol Configuration 2 */
1876 /*! @{ */
1877 
1878 #define FLEXRAY_PCR2_number_of_static_slots_MASK (0x3FFU)
1879 #define FLEXRAY_PCR2_number_of_static_slots_SHIFT (0U)
1880 #define FLEXRAY_PCR2_number_of_static_slots_WIDTH (10U)
1881 #define FLEXRAY_PCR2_number_of_static_slots(x)   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR2_number_of_static_slots_SHIFT)) & FLEXRAY_PCR2_number_of_static_slots_MASK)
1882 
1883 #define FLEXRAY_PCR2_minislot_after_action_point_MASK (0xFC00U)
1884 #define FLEXRAY_PCR2_minislot_after_action_point_SHIFT (10U)
1885 #define FLEXRAY_PCR2_minislot_after_action_point_WIDTH (6U)
1886 #define FLEXRAY_PCR2_minislot_after_action_point(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR2_minislot_after_action_point_SHIFT)) & FLEXRAY_PCR2_minislot_after_action_point_MASK)
1887 /*! @} */
1888 
1889 /*! @name PCR3 - Protocol Configuration 3 */
1890 /*! @{ */
1891 
1892 #define FLEXRAY_PCR3_coldstart_attempts_MASK     (0x1FU)
1893 #define FLEXRAY_PCR3_coldstart_attempts_SHIFT    (0U)
1894 #define FLEXRAY_PCR3_coldstart_attempts_WIDTH    (5U)
1895 #define FLEXRAY_PCR3_coldstart_attempts(x)       (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR3_coldstart_attempts_SHIFT)) & FLEXRAY_PCR3_coldstart_attempts_MASK)
1896 
1897 #define FLEXRAY_PCR3_minislot_action_point_offset_MASK (0x3E0U)
1898 #define FLEXRAY_PCR3_minislot_action_point_offset_SHIFT (5U)
1899 #define FLEXRAY_PCR3_minislot_action_point_offset_WIDTH (5U)
1900 #define FLEXRAY_PCR3_minislot_action_point_offset(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR3_minislot_action_point_offset_SHIFT)) & FLEXRAY_PCR3_minislot_action_point_offset_MASK)
1901 
1902 #define FLEXRAY_PCR3_wakeup_symbol_rx_low_MASK   (0xFC00U)
1903 #define FLEXRAY_PCR3_wakeup_symbol_rx_low_SHIFT  (10U)
1904 #define FLEXRAY_PCR3_wakeup_symbol_rx_low_WIDTH  (6U)
1905 #define FLEXRAY_PCR3_wakeup_symbol_rx_low(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR3_wakeup_symbol_rx_low_SHIFT)) & FLEXRAY_PCR3_wakeup_symbol_rx_low_MASK)
1906 /*! @} */
1907 
1908 /*! @name PCR4 - Protocol Configuration 4 */
1909 /*! @{ */
1910 
1911 #define FLEXRAY_PCR4_wakeup_symbol_rx_window_MASK (0x1FFU)
1912 #define FLEXRAY_PCR4_wakeup_symbol_rx_window_SHIFT (0U)
1913 #define FLEXRAY_PCR4_wakeup_symbol_rx_window_WIDTH (9U)
1914 #define FLEXRAY_PCR4_wakeup_symbol_rx_window(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR4_wakeup_symbol_rx_window_SHIFT)) & FLEXRAY_PCR4_wakeup_symbol_rx_window_MASK)
1915 
1916 #define FLEXRAY_PCR4_cas_rx_low_max_MASK         (0xFE00U)
1917 #define FLEXRAY_PCR4_cas_rx_low_max_SHIFT        (9U)
1918 #define FLEXRAY_PCR4_cas_rx_low_max_WIDTH        (7U)
1919 #define FLEXRAY_PCR4_cas_rx_low_max(x)           (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR4_cas_rx_low_max_SHIFT)) & FLEXRAY_PCR4_cas_rx_low_max_MASK)
1920 /*! @} */
1921 
1922 /*! @name PCR5 - Protocol Configuration 5 */
1923 /*! @{ */
1924 
1925 #define FLEXRAY_PCR5_wakeup_symbol_rx_idle_MASK  (0x3FU)
1926 #define FLEXRAY_PCR5_wakeup_symbol_rx_idle_SHIFT (0U)
1927 #define FLEXRAY_PCR5_wakeup_symbol_rx_idle_WIDTH (6U)
1928 #define FLEXRAY_PCR5_wakeup_symbol_rx_idle(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR5_wakeup_symbol_rx_idle_SHIFT)) & FLEXRAY_PCR5_wakeup_symbol_rx_idle_MASK)
1929 
1930 #define FLEXRAY_PCR5_wakeup_symbol_tx_low_MASK   (0xFC0U)
1931 #define FLEXRAY_PCR5_wakeup_symbol_tx_low_SHIFT  (6U)
1932 #define FLEXRAY_PCR5_wakeup_symbol_tx_low_WIDTH  (6U)
1933 #define FLEXRAY_PCR5_wakeup_symbol_tx_low(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR5_wakeup_symbol_tx_low_SHIFT)) & FLEXRAY_PCR5_wakeup_symbol_tx_low_MASK)
1934 
1935 #define FLEXRAY_PCR5_tss_transmitter_MASK        (0xF000U)
1936 #define FLEXRAY_PCR5_tss_transmitter_SHIFT       (12U)
1937 #define FLEXRAY_PCR5_tss_transmitter_WIDTH       (4U)
1938 #define FLEXRAY_PCR5_tss_transmitter(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR5_tss_transmitter_SHIFT)) & FLEXRAY_PCR5_tss_transmitter_MASK)
1939 /*! @} */
1940 
1941 /*! @name PCR6 - Protocol Configuration 6 */
1942 /*! @{ */
1943 
1944 #define FLEXRAY_PCR6_macro_initial_offset_a_MASK (0x7FU)
1945 #define FLEXRAY_PCR6_macro_initial_offset_a_SHIFT (0U)
1946 #define FLEXRAY_PCR6_macro_initial_offset_a_WIDTH (7U)
1947 #define FLEXRAY_PCR6_macro_initial_offset_a(x)   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR6_macro_initial_offset_a_SHIFT)) & FLEXRAY_PCR6_macro_initial_offset_a_MASK)
1948 
1949 #define FLEXRAY_PCR6_symbol_window_after_action_point_MASK (0x7F80U)
1950 #define FLEXRAY_PCR6_symbol_window_after_action_point_SHIFT (7U)
1951 #define FLEXRAY_PCR6_symbol_window_after_action_point_WIDTH (8U)
1952 #define FLEXRAY_PCR6_symbol_window_after_action_point(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR6_symbol_window_after_action_point_SHIFT)) & FLEXRAY_PCR6_symbol_window_after_action_point_MASK)
1953 /*! @} */
1954 
1955 /*! @name PCR7 - Protocol Configuration 7 */
1956 /*! @{ */
1957 
1958 #define FLEXRAY_PCR7_micro_per_macro_nom_half_MASK (0x7FU)
1959 #define FLEXRAY_PCR7_micro_per_macro_nom_half_SHIFT (0U)
1960 #define FLEXRAY_PCR7_micro_per_macro_nom_half_WIDTH (7U)
1961 #define FLEXRAY_PCR7_micro_per_macro_nom_half(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR7_micro_per_macro_nom_half_SHIFT)) & FLEXRAY_PCR7_micro_per_macro_nom_half_MASK)
1962 
1963 #define FLEXRAY_PCR7_decoding_correction_b_MASK  (0xFF80U)
1964 #define FLEXRAY_PCR7_decoding_correction_b_SHIFT (7U)
1965 #define FLEXRAY_PCR7_decoding_correction_b_WIDTH (9U)
1966 #define FLEXRAY_PCR7_decoding_correction_b(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR7_decoding_correction_b_SHIFT)) & FLEXRAY_PCR7_decoding_correction_b_MASK)
1967 /*! @} */
1968 
1969 /*! @name PCR8 - Protocol Configuration 8 */
1970 /*! @{ */
1971 
1972 #define FLEXRAY_PCR8_wakeup_symbol_tx_idle_MASK  (0xFFU)
1973 #define FLEXRAY_PCR8_wakeup_symbol_tx_idle_SHIFT (0U)
1974 #define FLEXRAY_PCR8_wakeup_symbol_tx_idle_WIDTH (8U)
1975 #define FLEXRAY_PCR8_wakeup_symbol_tx_idle(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR8_wakeup_symbol_tx_idle_SHIFT)) & FLEXRAY_PCR8_wakeup_symbol_tx_idle_MASK)
1976 
1977 #define FLEXRAY_PCR8_max_without_clock_correction_passive_MASK (0xF00U)
1978 #define FLEXRAY_PCR8_max_without_clock_correction_passive_SHIFT (8U)
1979 #define FLEXRAY_PCR8_max_without_clock_correction_passive_WIDTH (4U)
1980 #define FLEXRAY_PCR8_max_without_clock_correction_passive(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR8_max_without_clock_correction_passive_SHIFT)) & FLEXRAY_PCR8_max_without_clock_correction_passive_MASK)
1981 
1982 #define FLEXRAY_PCR8_max_without_clock_correction_fatal_MASK (0xF000U)
1983 #define FLEXRAY_PCR8_max_without_clock_correction_fatal_SHIFT (12U)
1984 #define FLEXRAY_PCR8_max_without_clock_correction_fatal_WIDTH (4U)
1985 #define FLEXRAY_PCR8_max_without_clock_correction_fatal(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR8_max_without_clock_correction_fatal_SHIFT)) & FLEXRAY_PCR8_max_without_clock_correction_fatal_MASK)
1986 /*! @} */
1987 
1988 /*! @name PCR9 - Protocol Configuration 9 */
1989 /*! @{ */
1990 
1991 #define FLEXRAY_PCR9_offset_correction_out_MASK  (0x3FFFU)
1992 #define FLEXRAY_PCR9_offset_correction_out_SHIFT (0U)
1993 #define FLEXRAY_PCR9_offset_correction_out_WIDTH (14U)
1994 #define FLEXRAY_PCR9_offset_correction_out(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR9_offset_correction_out_SHIFT)) & FLEXRAY_PCR9_offset_correction_out_MASK)
1995 
1996 #define FLEXRAY_PCR9_symbol_window_exists_MASK   (0x4000U)
1997 #define FLEXRAY_PCR9_symbol_window_exists_SHIFT  (14U)
1998 #define FLEXRAY_PCR9_symbol_window_exists_WIDTH  (1U)
1999 #define FLEXRAY_PCR9_symbol_window_exists(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR9_symbol_window_exists_SHIFT)) & FLEXRAY_PCR9_symbol_window_exists_MASK)
2000 
2001 #define FLEXRAY_PCR9_minislot_exists_MASK        (0x8000U)
2002 #define FLEXRAY_PCR9_minislot_exists_SHIFT       (15U)
2003 #define FLEXRAY_PCR9_minislot_exists_WIDTH       (1U)
2004 #define FLEXRAY_PCR9_minislot_exists(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR9_minislot_exists_SHIFT)) & FLEXRAY_PCR9_minislot_exists_MASK)
2005 /*! @} */
2006 
2007 /*! @name PCR10 - Protocol Configuration 10 */
2008 /*! @{ */
2009 
2010 #define FLEXRAY_PCR10_macro_per_cycle_MASK       (0x3FFFU)
2011 #define FLEXRAY_PCR10_macro_per_cycle_SHIFT      (0U)
2012 #define FLEXRAY_PCR10_macro_per_cycle_WIDTH      (14U)
2013 #define FLEXRAY_PCR10_macro_per_cycle(x)         (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR10_macro_per_cycle_SHIFT)) & FLEXRAY_PCR10_macro_per_cycle_MASK)
2014 
2015 #define FLEXRAY_PCR10_wakeup_channel_MASK        (0x4000U)
2016 #define FLEXRAY_PCR10_wakeup_channel_SHIFT       (14U)
2017 #define FLEXRAY_PCR10_wakeup_channel_WIDTH       (1U)
2018 #define FLEXRAY_PCR10_wakeup_channel(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR10_wakeup_channel_SHIFT)) & FLEXRAY_PCR10_wakeup_channel_MASK)
2019 
2020 #define FLEXRAY_PCR10_single_slot_enabled_MASK   (0x8000U)
2021 #define FLEXRAY_PCR10_single_slot_enabled_SHIFT  (15U)
2022 #define FLEXRAY_PCR10_single_slot_enabled_WIDTH  (1U)
2023 #define FLEXRAY_PCR10_single_slot_enabled(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR10_single_slot_enabled_SHIFT)) & FLEXRAY_PCR10_single_slot_enabled_MASK)
2024 /*! @} */
2025 
2026 /*! @name PCR11 - Protocol Configuration 11 */
2027 /*! @{ */
2028 
2029 #define FLEXRAY_PCR11_offset_correction_start_MASK (0x3FFFU)
2030 #define FLEXRAY_PCR11_offset_correction_start_SHIFT (0U)
2031 #define FLEXRAY_PCR11_offset_correction_start_WIDTH (14U)
2032 #define FLEXRAY_PCR11_offset_correction_start(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR11_offset_correction_start_SHIFT)) & FLEXRAY_PCR11_offset_correction_start_MASK)
2033 
2034 #define FLEXRAY_PCR11_key_slot_used_for_sync_MASK (0x4000U)
2035 #define FLEXRAY_PCR11_key_slot_used_for_sync_SHIFT (14U)
2036 #define FLEXRAY_PCR11_key_slot_used_for_sync_WIDTH (1U)
2037 #define FLEXRAY_PCR11_key_slot_used_for_sync(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR11_key_slot_used_for_sync_SHIFT)) & FLEXRAY_PCR11_key_slot_used_for_sync_MASK)
2038 
2039 #define FLEXRAY_PCR11_key_slot_used_for_startup_MASK (0x8000U)
2040 #define FLEXRAY_PCR11_key_slot_used_for_startup_SHIFT (15U)
2041 #define FLEXRAY_PCR11_key_slot_used_for_startup_WIDTH (1U)
2042 #define FLEXRAY_PCR11_key_slot_used_for_startup(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR11_key_slot_used_for_startup_SHIFT)) & FLEXRAY_PCR11_key_slot_used_for_startup_MASK)
2043 /*! @} */
2044 
2045 /*! @name PCR12 - Protocol Configuration 12 */
2046 /*! @{ */
2047 
2048 #define FLEXRAY_PCR12_key_slot_header_crc_MASK   (0x7FFU)
2049 #define FLEXRAY_PCR12_key_slot_header_crc_SHIFT  (0U)
2050 #define FLEXRAY_PCR12_key_slot_header_crc_WIDTH  (11U)
2051 #define FLEXRAY_PCR12_key_slot_header_crc(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR12_key_slot_header_crc_SHIFT)) & FLEXRAY_PCR12_key_slot_header_crc_MASK)
2052 
2053 #define FLEXRAY_PCR12_allow_passive_to_active_MASK (0xF800U)
2054 #define FLEXRAY_PCR12_allow_passive_to_active_SHIFT (11U)
2055 #define FLEXRAY_PCR12_allow_passive_to_active_WIDTH (5U)
2056 #define FLEXRAY_PCR12_allow_passive_to_active(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR12_allow_passive_to_active_SHIFT)) & FLEXRAY_PCR12_allow_passive_to_active_MASK)
2057 /*! @} */
2058 
2059 /*! @name PCR13 - Protocol Configuration 13 */
2060 /*! @{ */
2061 
2062 #define FLEXRAY_PCR13_static_slot_after_action_point_MASK (0x3FFU)
2063 #define FLEXRAY_PCR13_static_slot_after_action_point_SHIFT (0U)
2064 #define FLEXRAY_PCR13_static_slot_after_action_point_WIDTH (10U)
2065 #define FLEXRAY_PCR13_static_slot_after_action_point(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR13_static_slot_after_action_point_SHIFT)) & FLEXRAY_PCR13_static_slot_after_action_point_MASK)
2066 
2067 #define FLEXRAY_PCR13_first_minislot_action_point_offset_MASK (0xFC00U)
2068 #define FLEXRAY_PCR13_first_minislot_action_point_offset_SHIFT (10U)
2069 #define FLEXRAY_PCR13_first_minislot_action_point_offset_WIDTH (6U)
2070 #define FLEXRAY_PCR13_first_minislot_action_point_offset(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR13_first_minislot_action_point_offset_SHIFT)) & FLEXRAY_PCR13_first_minislot_action_point_offset_MASK)
2071 /*! @} */
2072 
2073 /*! @name PCR14 - Protocol Configuration 14 */
2074 /*! @{ */
2075 
2076 #define FLEXRAY_PCR14_listen_timeout_MASK        (0x1FU)
2077 #define FLEXRAY_PCR14_listen_timeout_SHIFT       (0U)
2078 #define FLEXRAY_PCR14_listen_timeout_WIDTH       (5U)
2079 #define FLEXRAY_PCR14_listen_timeout(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR14_listen_timeout_SHIFT)) & FLEXRAY_PCR14_listen_timeout_MASK)
2080 
2081 #define FLEXRAY_PCR14_rate_correction_out_MASK   (0xFFE0U)
2082 #define FLEXRAY_PCR14_rate_correction_out_SHIFT  (5U)
2083 #define FLEXRAY_PCR14_rate_correction_out_WIDTH  (11U)
2084 #define FLEXRAY_PCR14_rate_correction_out(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR14_rate_correction_out_SHIFT)) & FLEXRAY_PCR14_rate_correction_out_MASK)
2085 /*! @} */
2086 
2087 /*! @name PCR15 - Protocol Configuration 15 */
2088 /*! @{ */
2089 
2090 #define FLEXRAY_PCR15_listen_timeout_MASK        (0xFFFFU)
2091 #define FLEXRAY_PCR15_listen_timeout_SHIFT       (0U)
2092 #define FLEXRAY_PCR15_listen_timeout_WIDTH       (16U)
2093 #define FLEXRAY_PCR15_listen_timeout(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR15_listen_timeout_SHIFT)) & FLEXRAY_PCR15_listen_timeout_MASK)
2094 /*! @} */
2095 
2096 /*! @name PCR16 - Protocol Configuration 16 */
2097 /*! @{ */
2098 
2099 #define FLEXRAY_PCR16_noise_listen_timeout_MASK  (0x1FFU)
2100 #define FLEXRAY_PCR16_noise_listen_timeout_SHIFT (0U)
2101 #define FLEXRAY_PCR16_noise_listen_timeout_WIDTH (9U)
2102 #define FLEXRAY_PCR16_noise_listen_timeout(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR16_noise_listen_timeout_SHIFT)) & FLEXRAY_PCR16_noise_listen_timeout_MASK)
2103 
2104 #define FLEXRAY_PCR16_macro_initial_offset_b_MASK (0xFE00U)
2105 #define FLEXRAY_PCR16_macro_initial_offset_b_SHIFT (9U)
2106 #define FLEXRAY_PCR16_macro_initial_offset_b_WIDTH (7U)
2107 #define FLEXRAY_PCR16_macro_initial_offset_b(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR16_macro_initial_offset_b_SHIFT)) & FLEXRAY_PCR16_macro_initial_offset_b_MASK)
2108 /*! @} */
2109 
2110 /*! @name PCR17 - Protocol Configuration 17 */
2111 /*! @{ */
2112 
2113 #define FLEXRAY_PCR17_noise_listen_timeout_MASK  (0xFFFFU)
2114 #define FLEXRAY_PCR17_noise_listen_timeout_SHIFT (0U)
2115 #define FLEXRAY_PCR17_noise_listen_timeout_WIDTH (16U)
2116 #define FLEXRAY_PCR17_noise_listen_timeout(x)    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR17_noise_listen_timeout_SHIFT)) & FLEXRAY_PCR17_noise_listen_timeout_MASK)
2117 /*! @} */
2118 
2119 /*! @name PCR18 - Protocol Configuration 18 */
2120 /*! @{ */
2121 
2122 #define FLEXRAY_PCR18_key_slot_id_MASK           (0x3FFU)
2123 #define FLEXRAY_PCR18_key_slot_id_SHIFT          (0U)
2124 #define FLEXRAY_PCR18_key_slot_id_WIDTH          (10U)
2125 #define FLEXRAY_PCR18_key_slot_id(x)             (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR18_key_slot_id_SHIFT)) & FLEXRAY_PCR18_key_slot_id_MASK)
2126 
2127 #define FLEXRAY_PCR18_wakeup_pattern_MASK        (0xFC00U)
2128 #define FLEXRAY_PCR18_wakeup_pattern_SHIFT       (10U)
2129 #define FLEXRAY_PCR18_wakeup_pattern_WIDTH       (6U)
2130 #define FLEXRAY_PCR18_wakeup_pattern(x)          (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR18_wakeup_pattern_SHIFT)) & FLEXRAY_PCR18_wakeup_pattern_MASK)
2131 /*! @} */
2132 
2133 /*! @name PCR19 - Protocol Configuration 19 */
2134 /*! @{ */
2135 
2136 #define FLEXRAY_PCR19_payload_length_static_MASK (0x7FU)
2137 #define FLEXRAY_PCR19_payload_length_static_SHIFT (0U)
2138 #define FLEXRAY_PCR19_payload_length_static_WIDTH (7U)
2139 #define FLEXRAY_PCR19_payload_length_static(x)   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR19_payload_length_static_SHIFT)) & FLEXRAY_PCR19_payload_length_static_MASK)
2140 
2141 #define FLEXRAY_PCR19_decoding_correction_a_MASK (0xFF80U)
2142 #define FLEXRAY_PCR19_decoding_correction_a_SHIFT (7U)
2143 #define FLEXRAY_PCR19_decoding_correction_a_WIDTH (9U)
2144 #define FLEXRAY_PCR19_decoding_correction_a(x)   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR19_decoding_correction_a_SHIFT)) & FLEXRAY_PCR19_decoding_correction_a_MASK)
2145 /*! @} */
2146 
2147 /*! @name PCR20 - Protocol Configuration 20 */
2148 /*! @{ */
2149 
2150 #define FLEXRAY_PCR20_micro_initial_offset_a_MASK (0xFFU)
2151 #define FLEXRAY_PCR20_micro_initial_offset_a_SHIFT (0U)
2152 #define FLEXRAY_PCR20_micro_initial_offset_a_WIDTH (8U)
2153 #define FLEXRAY_PCR20_micro_initial_offset_a(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR20_micro_initial_offset_a_SHIFT)) & FLEXRAY_PCR20_micro_initial_offset_a_MASK)
2154 
2155 #define FLEXRAY_PCR20_micro_initial_offset_b_MASK (0xFF00U)
2156 #define FLEXRAY_PCR20_micro_initial_offset_b_SHIFT (8U)
2157 #define FLEXRAY_PCR20_micro_initial_offset_b_WIDTH (8U)
2158 #define FLEXRAY_PCR20_micro_initial_offset_b(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR20_micro_initial_offset_b_SHIFT)) & FLEXRAY_PCR20_micro_initial_offset_b_MASK)
2159 /*! @} */
2160 
2161 /*! @name PCR21 - Protocol Configuration 21 */
2162 /*! @{ */
2163 
2164 #define FLEXRAY_PCR21_latest_tx_MASK             (0x1FFFU)
2165 #define FLEXRAY_PCR21_latest_tx_SHIFT            (0U)
2166 #define FLEXRAY_PCR21_latest_tx_WIDTH            (13U)
2167 #define FLEXRAY_PCR21_latest_tx(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR21_latest_tx_SHIFT)) & FLEXRAY_PCR21_latest_tx_MASK)
2168 
2169 #define FLEXRAY_PCR21_extern_rate_correction_MASK (0xE000U)
2170 #define FLEXRAY_PCR21_extern_rate_correction_SHIFT (13U)
2171 #define FLEXRAY_PCR21_extern_rate_correction_WIDTH (3U)
2172 #define FLEXRAY_PCR21_extern_rate_correction(x)  (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR21_extern_rate_correction_SHIFT)) & FLEXRAY_PCR21_extern_rate_correction_MASK)
2173 /*! @} */
2174 
2175 /*! @name PCR22 - Protocol Configuration 22 */
2176 /*! @{ */
2177 
2178 #define FLEXRAY_PCR22_micro_per_cycle_MASK       (0xFU)
2179 #define FLEXRAY_PCR22_micro_per_cycle_SHIFT      (0U)
2180 #define FLEXRAY_PCR22_micro_per_cycle_WIDTH      (4U)
2181 #define FLEXRAY_PCR22_micro_per_cycle(x)         (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR22_micro_per_cycle_SHIFT)) & FLEXRAY_PCR22_micro_per_cycle_MASK)
2182 
2183 #define FLEXRAY_PCR22_comp_accepted_startup_range_a_MASK (0x7FF0U)
2184 #define FLEXRAY_PCR22_comp_accepted_startup_range_a_SHIFT (4U)
2185 #define FLEXRAY_PCR22_comp_accepted_startup_range_a_WIDTH (11U)
2186 #define FLEXRAY_PCR22_comp_accepted_startup_range_a(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR22_comp_accepted_startup_range_a_SHIFT)) & FLEXRAY_PCR22_comp_accepted_startup_range_a_MASK)
2187 /*! @} */
2188 
2189 /*! @name PCR23 - Protocol Configuration 23 */
2190 /*! @{ */
2191 
2192 #define FLEXRAY_PCR23_micro_per_cycle_MASK       (0xFFFFU)
2193 #define FLEXRAY_PCR23_micro_per_cycle_SHIFT      (0U)
2194 #define FLEXRAY_PCR23_micro_per_cycle_WIDTH      (16U)
2195 #define FLEXRAY_PCR23_micro_per_cycle(x)         (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR23_micro_per_cycle_SHIFT)) & FLEXRAY_PCR23_micro_per_cycle_MASK)
2196 /*! @} */
2197 
2198 /*! @name PCR24 - Protocol Configuration 24 */
2199 /*! @{ */
2200 
2201 #define FLEXRAY_PCR24_micro_per_cycle_min_MASK   (0xFU)
2202 #define FLEXRAY_PCR24_micro_per_cycle_min_SHIFT  (0U)
2203 #define FLEXRAY_PCR24_micro_per_cycle_min_WIDTH  (4U)
2204 #define FLEXRAY_PCR24_micro_per_cycle_min(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR24_micro_per_cycle_min_SHIFT)) & FLEXRAY_PCR24_micro_per_cycle_min_MASK)
2205 
2206 #define FLEXRAY_PCR24_max_payload_length_dynamic_MASK (0x7F0U)
2207 #define FLEXRAY_PCR24_max_payload_length_dynamic_SHIFT (4U)
2208 #define FLEXRAY_PCR24_max_payload_length_dynamic_WIDTH (7U)
2209 #define FLEXRAY_PCR24_max_payload_length_dynamic(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR24_max_payload_length_dynamic_SHIFT)) & FLEXRAY_PCR24_max_payload_length_dynamic_MASK)
2210 
2211 #define FLEXRAY_PCR24_cluster_drift_damping_MASK (0xF800U)
2212 #define FLEXRAY_PCR24_cluster_drift_damping_SHIFT (11U)
2213 #define FLEXRAY_PCR24_cluster_drift_damping_WIDTH (5U)
2214 #define FLEXRAY_PCR24_cluster_drift_damping(x)   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR24_cluster_drift_damping_SHIFT)) & FLEXRAY_PCR24_cluster_drift_damping_MASK)
2215 /*! @} */
2216 
2217 /*! @name PCR25 - Protocol Configuration 25 */
2218 /*! @{ */
2219 
2220 #define FLEXRAY_PCR25_micro_per_cycle_min_MASK   (0xFFFFU)
2221 #define FLEXRAY_PCR25_micro_per_cycle_min_SHIFT  (0U)
2222 #define FLEXRAY_PCR25_micro_per_cycle_min_WIDTH  (16U)
2223 #define FLEXRAY_PCR25_micro_per_cycle_min(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR25_micro_per_cycle_min_SHIFT)) & FLEXRAY_PCR25_micro_per_cycle_min_MASK)
2224 /*! @} */
2225 
2226 /*! @name PCR26 - Protocol Configuration 26 */
2227 /*! @{ */
2228 
2229 #define FLEXRAY_PCR26_micro_per_cycle_max_MASK   (0xFU)
2230 #define FLEXRAY_PCR26_micro_per_cycle_max_SHIFT  (0U)
2231 #define FLEXRAY_PCR26_micro_per_cycle_max_WIDTH  (4U)
2232 #define FLEXRAY_PCR26_micro_per_cycle_max(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR26_micro_per_cycle_max_SHIFT)) & FLEXRAY_PCR26_micro_per_cycle_max_MASK)
2233 
2234 #define FLEXRAY_PCR26_comp_accepted_startup_range_b_MASK (0x7FF0U)
2235 #define FLEXRAY_PCR26_comp_accepted_startup_range_b_SHIFT (4U)
2236 #define FLEXRAY_PCR26_comp_accepted_startup_range_b_WIDTH (11U)
2237 #define FLEXRAY_PCR26_comp_accepted_startup_range_b(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR26_comp_accepted_startup_range_b_SHIFT)) & FLEXRAY_PCR26_comp_accepted_startup_range_b_MASK)
2238 
2239 #define FLEXRAY_PCR26_allow_halt_due_to_clock_MASK (0x8000U)
2240 #define FLEXRAY_PCR26_allow_halt_due_to_clock_SHIFT (15U)
2241 #define FLEXRAY_PCR26_allow_halt_due_to_clock_WIDTH (1U)
2242 #define FLEXRAY_PCR26_allow_halt_due_to_clock(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR26_allow_halt_due_to_clock_SHIFT)) & FLEXRAY_PCR26_allow_halt_due_to_clock_MASK)
2243 /*! @} */
2244 
2245 /*! @name PCR27 - Protocol Configuration 27 */
2246 /*! @{ */
2247 
2248 #define FLEXRAY_PCR27_micro_per_cycle_max_MASK   (0xFFFFU)
2249 #define FLEXRAY_PCR27_micro_per_cycle_max_SHIFT  (0U)
2250 #define FLEXRAY_PCR27_micro_per_cycle_max_WIDTH  (16U)
2251 #define FLEXRAY_PCR27_micro_per_cycle_max(x)     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR27_micro_per_cycle_max_SHIFT)) & FLEXRAY_PCR27_micro_per_cycle_max_MASK)
2252 /*! @} */
2253 
2254 /*! @name PCR28 - Protocol Configuration 28 */
2255 /*! @{ */
2256 
2257 #define FLEXRAY_PCR28_macro_after_offset_correction_MASK (0x3FFFU)
2258 #define FLEXRAY_PCR28_macro_after_offset_correction_SHIFT (0U)
2259 #define FLEXRAY_PCR28_macro_after_offset_correction_WIDTH (14U)
2260 #define FLEXRAY_PCR28_macro_after_offset_correction(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR28_macro_after_offset_correction_SHIFT)) & FLEXRAY_PCR28_macro_after_offset_correction_MASK)
2261 
2262 #define FLEXRAY_PCR28_dynamic_slot_idle_phase_MASK (0xC000U)
2263 #define FLEXRAY_PCR28_dynamic_slot_idle_phase_SHIFT (14U)
2264 #define FLEXRAY_PCR28_dynamic_slot_idle_phase_WIDTH (2U)
2265 #define FLEXRAY_PCR28_dynamic_slot_idle_phase(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR28_dynamic_slot_idle_phase_SHIFT)) & FLEXRAY_PCR28_dynamic_slot_idle_phase_MASK)
2266 /*! @} */
2267 
2268 /*! @name PCR29 - Protocol Configuration 29 */
2269 /*! @{ */
2270 
2271 #define FLEXRAY_PCR29_minislots_max_MASK         (0x1FFFU)
2272 #define FLEXRAY_PCR29_minislots_max_SHIFT        (0U)
2273 #define FLEXRAY_PCR29_minislots_max_WIDTH        (13U)
2274 #define FLEXRAY_PCR29_minislots_max(x)           (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR29_minislots_max_SHIFT)) & FLEXRAY_PCR29_minislots_max_MASK)
2275 
2276 #define FLEXRAY_PCR29_extern_offset_correction_MASK (0xE000U)
2277 #define FLEXRAY_PCR29_extern_offset_correction_SHIFT (13U)
2278 #define FLEXRAY_PCR29_extern_offset_correction_WIDTH (3U)
2279 #define FLEXRAY_PCR29_extern_offset_correction(x) (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR29_extern_offset_correction_SHIFT)) & FLEXRAY_PCR29_extern_offset_correction_MASK)
2280 /*! @} */
2281 
2282 /*! @name PCR30 - Protocol Configuration 30 */
2283 /*! @{ */
2284 
2285 #define FLEXRAY_PCR30_sync_node_max_MASK         (0xFU)
2286 #define FLEXRAY_PCR30_sync_node_max_SHIFT        (0U)
2287 #define FLEXRAY_PCR30_sync_node_max_WIDTH        (4U)
2288 #define FLEXRAY_PCR30_sync_node_max(x)           (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PCR30_sync_node_max_SHIFT)) & FLEXRAY_PCR30_sync_node_max_MASK)
2289 /*! @} */
2290 
2291 /*! @name STPWHR - Stopwatch Count High */
2292 /*! @{ */
2293 
2294 #define FLEXRAY_STPWHR_STPW_S_H_MASK             (0xFFFFU)
2295 #define FLEXRAY_STPWHR_STPW_S_H_SHIFT            (0U)
2296 #define FLEXRAY_STPWHR_STPW_S_H_WIDTH            (16U)
2297 #define FLEXRAY_STPWHR_STPW_S_H(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STPWHR_STPW_S_H_SHIFT)) & FLEXRAY_STPWHR_STPW_S_H_MASK)
2298 /*! @} */
2299 
2300 /*! @name STPWLR - Stopwatch Count Low */
2301 /*! @{ */
2302 
2303 #define FLEXRAY_STPWLR_STPW_S_L_MASK             (0xFFFFU)
2304 #define FLEXRAY_STPWLR_STPW_S_L_SHIFT            (0U)
2305 #define FLEXRAY_STPWLR_STPW_S_L_WIDTH            (16U)
2306 #define FLEXRAY_STPWLR_STPW_S_L(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_STPWLR_STPW_S_L_SHIFT)) & FLEXRAY_STPWLR_STPW_S_L_MASK)
2307 /*! @} */
2308 
2309 /*! @name PEOER - Protocol Event Output Enable And Stopwatch Control */
2310 /*! @{ */
2311 
2312 #define FLEXRAY_PEOER_STPW_EN_MASK               (0x100U)
2313 #define FLEXRAY_PEOER_STPW_EN_SHIFT              (8U)
2314 #define FLEXRAY_PEOER_STPW_EN_WIDTH              (1U)
2315 #define FLEXRAY_PEOER_STPW_EN(x)                 (((uint16_t)(((uint16_t)(x)) << FLEXRAY_PEOER_STPW_EN_SHIFT)) & FLEXRAY_PEOER_STPW_EN_MASK)
2316 /*! @} */
2317 
2318 /*! @name RFSDOR - Receive FIFO Start Data Offset */
2319 /*! @{ */
2320 
2321 #define FLEXRAY_RFSDOR_SDO_MASK                  (0xFFFFU)
2322 #define FLEXRAY_RFSDOR_SDO_SHIFT                 (0U)
2323 #define FLEXRAY_RFSDOR_SDO_WIDTH                 (16U)
2324 #define FLEXRAY_RFSDOR_SDO(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFSDOR_SDO_SHIFT)) & FLEXRAY_RFSDOR_SDO_MASK)
2325 /*! @} */
2326 
2327 /*! @name RFSYMBADHR - Receive FIFO System Memory Base Address High */
2328 /*! @{ */
2329 
2330 #define FLEXRAY_RFSYMBADHR_SMBA_MASK             (0xFFFFU)
2331 #define FLEXRAY_RFSYMBADHR_SMBA_SHIFT            (0U)
2332 #define FLEXRAY_RFSYMBADHR_SMBA_WIDTH            (16U)
2333 #define FLEXRAY_RFSYMBADHR_SMBA(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFSYMBADHR_SMBA_SHIFT)) & FLEXRAY_RFSYMBADHR_SMBA_MASK)
2334 /*! @} */
2335 
2336 /*! @name RFSYMBADLR - Receive FIFO System Memory Base Address Low */
2337 /*! @{ */
2338 
2339 #define FLEXRAY_RFSYMBADLR_SMBA_MASK             (0xFFF0U)
2340 #define FLEXRAY_RFSYMBADLR_SMBA_SHIFT            (4U)
2341 #define FLEXRAY_RFSYMBADLR_SMBA_WIDTH            (12U)
2342 #define FLEXRAY_RFSYMBADLR_SMBA(x)               (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFSYMBADLR_SMBA_SHIFT)) & FLEXRAY_RFSYMBADLR_SMBA_MASK)
2343 /*! @} */
2344 
2345 /*! @name RFPTR - Receive FIFO Periodic Timer */
2346 /*! @{ */
2347 
2348 #define FLEXRAY_RFPTR_PTD_MASK                   (0x3FFFU)
2349 #define FLEXRAY_RFPTR_PTD_SHIFT                  (0U)
2350 #define FLEXRAY_RFPTR_PTD_WIDTH                  (14U)
2351 #define FLEXRAY_RFPTR_PTD(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFPTR_PTD_SHIFT)) & FLEXRAY_RFPTR_PTD_MASK)
2352 /*! @} */
2353 
2354 /*! @name RFFLPCR - Receive FIFO Fill Level and Pop Count */
2355 /*! @{ */
2356 
2357 #define FLEXRAY_RFFLPCR_FLA_or_PCA_MASK          (0xFFU)
2358 #define FLEXRAY_RFFLPCR_FLA_or_PCA_SHIFT         (0U)
2359 #define FLEXRAY_RFFLPCR_FLA_or_PCA_WIDTH         (8U)
2360 #define FLEXRAY_RFFLPCR_FLA_or_PCA(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFFLPCR_FLA_or_PCA_SHIFT)) & FLEXRAY_RFFLPCR_FLA_or_PCA_MASK)
2361 
2362 #define FLEXRAY_RFFLPCR_FLB_or_PCB_MASK          (0xFF00U)
2363 #define FLEXRAY_RFFLPCR_FLB_or_PCB_SHIFT         (8U)
2364 #define FLEXRAY_RFFLPCR_FLB_or_PCB_WIDTH         (8U)
2365 #define FLEXRAY_RFFLPCR_FLB_or_PCB(x)            (((uint16_t)(((uint16_t)(x)) << FLEXRAY_RFFLPCR_FLB_or_PCB_SHIFT)) & FLEXRAY_RFFLPCR_FLB_or_PCB_MASK)
2366 /*! @} */
2367 
2368 /*! @name EEIFER - ECC Error Interrupt Flag And Enable */
2369 /*! @{ */
2370 
2371 #define FLEXRAY_EEIFER_DRCE_IE_MASK              (0x1U)
2372 #define FLEXRAY_EEIFER_DRCE_IE_SHIFT             (0U)
2373 #define FLEXRAY_EEIFER_DRCE_IE_WIDTH             (1U)
2374 #define FLEXRAY_EEIFER_DRCE_IE(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRCE_IE_SHIFT)) & FLEXRAY_EEIFER_DRCE_IE_MASK)
2375 
2376 #define FLEXRAY_EEIFER_DRNE_IE_MASK              (0x2U)
2377 #define FLEXRAY_EEIFER_DRNE_IE_SHIFT             (1U)
2378 #define FLEXRAY_EEIFER_DRNE_IE_WIDTH             (1U)
2379 #define FLEXRAY_EEIFER_DRNE_IE(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRNE_IE_SHIFT)) & FLEXRAY_EEIFER_DRNE_IE_MASK)
2380 
2381 #define FLEXRAY_EEIFER_LRCE_IE_MASK              (0x4U)
2382 #define FLEXRAY_EEIFER_LRCE_IE_SHIFT             (2U)
2383 #define FLEXRAY_EEIFER_LRCE_IE_WIDTH             (1U)
2384 #define FLEXRAY_EEIFER_LRCE_IE(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRCE_IE_SHIFT)) & FLEXRAY_EEIFER_LRCE_IE_MASK)
2385 
2386 #define FLEXRAY_EEIFER_LRNE_IE_MASK              (0x8U)
2387 #define FLEXRAY_EEIFER_LRNE_IE_SHIFT             (3U)
2388 #define FLEXRAY_EEIFER_LRNE_IE_WIDTH             (1U)
2389 #define FLEXRAY_EEIFER_LRNE_IE(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRNE_IE_SHIFT)) & FLEXRAY_EEIFER_LRNE_IE_MASK)
2390 
2391 #define FLEXRAY_EEIFER_DRCE_IF_MASK              (0x100U)
2392 #define FLEXRAY_EEIFER_DRCE_IF_SHIFT             (8U)
2393 #define FLEXRAY_EEIFER_DRCE_IF_WIDTH             (1U)
2394 #define FLEXRAY_EEIFER_DRCE_IF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRCE_IF_SHIFT)) & FLEXRAY_EEIFER_DRCE_IF_MASK)
2395 
2396 #define FLEXRAY_EEIFER_DRNE_IF_MASK              (0x200U)
2397 #define FLEXRAY_EEIFER_DRNE_IF_SHIFT             (9U)
2398 #define FLEXRAY_EEIFER_DRNE_IF_WIDTH             (1U)
2399 #define FLEXRAY_EEIFER_DRNE_IF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRNE_IF_SHIFT)) & FLEXRAY_EEIFER_DRNE_IF_MASK)
2400 
2401 #define FLEXRAY_EEIFER_LRCE_IF_MASK              (0x400U)
2402 #define FLEXRAY_EEIFER_LRCE_IF_SHIFT             (10U)
2403 #define FLEXRAY_EEIFER_LRCE_IF_WIDTH             (1U)
2404 #define FLEXRAY_EEIFER_LRCE_IF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRCE_IF_SHIFT)) & FLEXRAY_EEIFER_LRCE_IF_MASK)
2405 
2406 #define FLEXRAY_EEIFER_LRNE_IF_MASK              (0x800U)
2407 #define FLEXRAY_EEIFER_LRNE_IF_SHIFT             (11U)
2408 #define FLEXRAY_EEIFER_LRNE_IF_WIDTH             (1U)
2409 #define FLEXRAY_EEIFER_LRNE_IF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRNE_IF_SHIFT)) & FLEXRAY_EEIFER_LRNE_IF_MASK)
2410 
2411 #define FLEXRAY_EEIFER_DRCE_OF_MASK              (0x1000U)
2412 #define FLEXRAY_EEIFER_DRCE_OF_SHIFT             (12U)
2413 #define FLEXRAY_EEIFER_DRCE_OF_WIDTH             (1U)
2414 #define FLEXRAY_EEIFER_DRCE_OF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRCE_OF_SHIFT)) & FLEXRAY_EEIFER_DRCE_OF_MASK)
2415 
2416 #define FLEXRAY_EEIFER_DRNE_OF_MASK              (0x2000U)
2417 #define FLEXRAY_EEIFER_DRNE_OF_SHIFT             (13U)
2418 #define FLEXRAY_EEIFER_DRNE_OF_WIDTH             (1U)
2419 #define FLEXRAY_EEIFER_DRNE_OF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_DRNE_OF_SHIFT)) & FLEXRAY_EEIFER_DRNE_OF_MASK)
2420 
2421 #define FLEXRAY_EEIFER_LRCE_OF_MASK              (0x4000U)
2422 #define FLEXRAY_EEIFER_LRCE_OF_SHIFT             (14U)
2423 #define FLEXRAY_EEIFER_LRCE_OF_WIDTH             (1U)
2424 #define FLEXRAY_EEIFER_LRCE_OF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRCE_OF_SHIFT)) & FLEXRAY_EEIFER_LRCE_OF_MASK)
2425 
2426 #define FLEXRAY_EEIFER_LRNE_OF_MASK              (0x8000U)
2427 #define FLEXRAY_EEIFER_LRNE_OF_SHIFT             (15U)
2428 #define FLEXRAY_EEIFER_LRNE_OF_WIDTH             (1U)
2429 #define FLEXRAY_EEIFER_LRNE_OF(x)                (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIFER_LRNE_OF_SHIFT)) & FLEXRAY_EEIFER_LRNE_OF_MASK)
2430 /*! @} */
2431 
2432 /*! @name EERICR - ECC Error Report And Injection Control */
2433 /*! @{ */
2434 
2435 #define FLEXRAY_EERICR_EIE_MASK                  (0x1U)
2436 #define FLEXRAY_EERICR_EIE_SHIFT                 (0U)
2437 #define FLEXRAY_EERICR_EIE_WIDTH                 (1U)
2438 #define FLEXRAY_EERICR_EIE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERICR_EIE_SHIFT)) & FLEXRAY_EERICR_EIE_MASK)
2439 
2440 #define FLEXRAY_EERICR_EIM_MASK                  (0x2U)
2441 #define FLEXRAY_EERICR_EIM_SHIFT                 (1U)
2442 #define FLEXRAY_EERICR_EIM_WIDTH                 (1U)
2443 #define FLEXRAY_EERICR_EIM(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERICR_EIM_SHIFT)) & FLEXRAY_EERICR_EIM_MASK)
2444 
2445 #define FLEXRAY_EERICR_ERM_MASK                  (0x10U)
2446 #define FLEXRAY_EERICR_ERM_SHIFT                 (4U)
2447 #define FLEXRAY_EERICR_ERM_WIDTH                 (1U)
2448 #define FLEXRAY_EERICR_ERM(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERICR_ERM_SHIFT)) & FLEXRAY_EERICR_ERM_MASK)
2449 
2450 #define FLEXRAY_EERICR_ERS_MASK                  (0x300U)
2451 #define FLEXRAY_EERICR_ERS_SHIFT                 (8U)
2452 #define FLEXRAY_EERICR_ERS_WIDTH                 (2U)
2453 #define FLEXRAY_EERICR_ERS(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERICR_ERS_SHIFT)) & FLEXRAY_EERICR_ERS_MASK)
2454 
2455 #define FLEXRAY_EERICR_BSY_MASK                  (0x8000U)
2456 #define FLEXRAY_EERICR_BSY_SHIFT                 (15U)
2457 #define FLEXRAY_EERICR_BSY_WIDTH                 (1U)
2458 #define FLEXRAY_EERICR_BSY(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERICR_BSY_SHIFT)) & FLEXRAY_EERICR_BSY_MASK)
2459 /*! @} */
2460 
2461 /*! @name EERAR - ECC Error Report Address */
2462 /*! @{ */
2463 
2464 #define FLEXRAY_EERAR_ADDR_MASK                  (0xFFFU)
2465 #define FLEXRAY_EERAR_ADDR_SHIFT                 (0U)
2466 #define FLEXRAY_EERAR_ADDR_WIDTH                 (12U)
2467 #define FLEXRAY_EERAR_ADDR(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERAR_ADDR_SHIFT)) & FLEXRAY_EERAR_ADDR_MASK)
2468 
2469 #define FLEXRAY_EERAR_BANK_MASK                  (0x7000U)
2470 #define FLEXRAY_EERAR_BANK_SHIFT                 (12U)
2471 #define FLEXRAY_EERAR_BANK_WIDTH                 (3U)
2472 #define FLEXRAY_EERAR_BANK(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERAR_BANK_SHIFT)) & FLEXRAY_EERAR_BANK_MASK)
2473 
2474 #define FLEXRAY_EERAR_MID_MASK                   (0x8000U)
2475 #define FLEXRAY_EERAR_MID_SHIFT                  (15U)
2476 #define FLEXRAY_EERAR_MID_WIDTH                  (1U)
2477 #define FLEXRAY_EERAR_MID(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERAR_MID_SHIFT)) & FLEXRAY_EERAR_MID_MASK)
2478 /*! @} */
2479 
2480 /*! @name EERDR - ECC Error Report Data */
2481 /*! @{ */
2482 
2483 #define FLEXRAY_EERDR_DATA_MASK                  (0xFFFFU)
2484 #define FLEXRAY_EERDR_DATA_SHIFT                 (0U)
2485 #define FLEXRAY_EERDR_DATA_WIDTH                 (16U)
2486 #define FLEXRAY_EERDR_DATA(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERDR_DATA_SHIFT)) & FLEXRAY_EERDR_DATA_MASK)
2487 /*! @} */
2488 
2489 /*! @name EERCR - ECC Error Report Code */
2490 /*! @{ */
2491 
2492 #define FLEXRAY_EERCR_CODE_MASK                  (0x1FU)
2493 #define FLEXRAY_EERCR_CODE_SHIFT                 (0U)
2494 #define FLEXRAY_EERCR_CODE_WIDTH                 (5U)
2495 #define FLEXRAY_EERCR_CODE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EERCR_CODE_SHIFT)) & FLEXRAY_EERCR_CODE_MASK)
2496 /*! @} */
2497 
2498 /*! @name EEIAR - ECC Error Injection Address */
2499 /*! @{ */
2500 
2501 #define FLEXRAY_EEIAR_ADDR_MASK                  (0xFFFU)
2502 #define FLEXRAY_EEIAR_ADDR_SHIFT                 (0U)
2503 #define FLEXRAY_EEIAR_ADDR_WIDTH                 (12U)
2504 #define FLEXRAY_EEIAR_ADDR(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIAR_ADDR_SHIFT)) & FLEXRAY_EEIAR_ADDR_MASK)
2505 
2506 #define FLEXRAY_EEIAR_BANK_MASK                  (0x7000U)
2507 #define FLEXRAY_EEIAR_BANK_SHIFT                 (12U)
2508 #define FLEXRAY_EEIAR_BANK_WIDTH                 (3U)
2509 #define FLEXRAY_EEIAR_BANK(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIAR_BANK_SHIFT)) & FLEXRAY_EEIAR_BANK_MASK)
2510 
2511 #define FLEXRAY_EEIAR_MID_MASK                   (0x8000U)
2512 #define FLEXRAY_EEIAR_MID_SHIFT                  (15U)
2513 #define FLEXRAY_EEIAR_MID_WIDTH                  (1U)
2514 #define FLEXRAY_EEIAR_MID(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIAR_MID_SHIFT)) & FLEXRAY_EEIAR_MID_MASK)
2515 /*! @} */
2516 
2517 /*! @name EEIDR - ECC Error Injection Data */
2518 /*! @{ */
2519 
2520 #define FLEXRAY_EEIDR_DATA_MASK                  (0xFFFFU)
2521 #define FLEXRAY_EEIDR_DATA_SHIFT                 (0U)
2522 #define FLEXRAY_EEIDR_DATA_WIDTH                 (16U)
2523 #define FLEXRAY_EEIDR_DATA(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEIDR_DATA_SHIFT)) & FLEXRAY_EEIDR_DATA_MASK)
2524 /*! @} */
2525 
2526 /*! @name EEICR - ECC Error Injection Code */
2527 /*! @{ */
2528 
2529 #define FLEXRAY_EEICR_CODE_MASK                  (0x1FU)
2530 #define FLEXRAY_EEICR_CODE_SHIFT                 (0U)
2531 #define FLEXRAY_EEICR_CODE_WIDTH                 (5U)
2532 #define FLEXRAY_EEICR_CODE(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_EEICR_CODE_SHIFT)) & FLEXRAY_EEICR_CODE_MASK)
2533 /*! @} */
2534 
2535 /*! @name CCSR - MB Configuration Control Status */
2536 /*! @{ */
2537 
2538 #define FLEXRAY_CCSR_MBIF_MASK                   (0x1U)
2539 #define FLEXRAY_CCSR_MBIF_SHIFT                  (0U)
2540 #define FLEXRAY_CCSR_MBIF_WIDTH                  (1U)
2541 #define FLEXRAY_CCSR_MBIF(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_MBIF_SHIFT)) & FLEXRAY_CCSR_MBIF_MASK)
2542 
2543 #define FLEXRAY_CCSR_LCKS_MASK                   (0x2U)
2544 #define FLEXRAY_CCSR_LCKS_SHIFT                  (1U)
2545 #define FLEXRAY_CCSR_LCKS_WIDTH                  (1U)
2546 #define FLEXRAY_CCSR_LCKS(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_LCKS_SHIFT)) & FLEXRAY_CCSR_LCKS_MASK)
2547 
2548 #define FLEXRAY_CCSR_EDS_MASK                    (0x4U)
2549 #define FLEXRAY_CCSR_EDS_SHIFT                   (2U)
2550 #define FLEXRAY_CCSR_EDS_WIDTH                   (1U)
2551 #define FLEXRAY_CCSR_EDS(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_EDS_SHIFT)) & FLEXRAY_CCSR_EDS_MASK)
2552 
2553 #define FLEXRAY_CCSR_DVAL_MASK                   (0x8U)
2554 #define FLEXRAY_CCSR_DVAL_SHIFT                  (3U)
2555 #define FLEXRAY_CCSR_DVAL_WIDTH                  (1U)
2556 #define FLEXRAY_CCSR_DVAL(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_DVAL_SHIFT)) & FLEXRAY_CCSR_DVAL_MASK)
2557 
2558 #define FLEXRAY_CCSR_DUP_MASK                    (0x10U)
2559 #define FLEXRAY_CCSR_DUP_SHIFT                   (4U)
2560 #define FLEXRAY_CCSR_DUP_WIDTH                   (1U)
2561 #define FLEXRAY_CCSR_DUP(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_DUP_SHIFT)) & FLEXRAY_CCSR_DUP_MASK)
2562 
2563 #define FLEXRAY_CCSR_MBIE_MASK                   (0x100U)
2564 #define FLEXRAY_CCSR_MBIE_SHIFT                  (8U)
2565 #define FLEXRAY_CCSR_MBIE_WIDTH                  (1U)
2566 #define FLEXRAY_CCSR_MBIE(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_MBIE_SHIFT)) & FLEXRAY_CCSR_MBIE_MASK)
2567 
2568 #define FLEXRAY_CCSR_LCKT_MASK                   (0x200U)
2569 #define FLEXRAY_CCSR_LCKT_SHIFT                  (9U)
2570 #define FLEXRAY_CCSR_LCKT_WIDTH                  (1U)
2571 #define FLEXRAY_CCSR_LCKT(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_LCKT_SHIFT)) & FLEXRAY_CCSR_LCKT_MASK)
2572 
2573 #define FLEXRAY_CCSR_EDT_MASK                    (0x400U)
2574 #define FLEXRAY_CCSR_EDT_SHIFT                   (10U)
2575 #define FLEXRAY_CCSR_EDT_WIDTH                   (1U)
2576 #define FLEXRAY_CCSR_EDT(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_EDT_SHIFT)) & FLEXRAY_CCSR_EDT_MASK)
2577 
2578 #define FLEXRAY_CCSR_CMT_MASK                    (0x800U)
2579 #define FLEXRAY_CCSR_CMT_SHIFT                   (11U)
2580 #define FLEXRAY_CCSR_CMT_WIDTH                   (1U)
2581 #define FLEXRAY_CCSR_CMT(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_CMT_SHIFT)) & FLEXRAY_CCSR_CMT_MASK)
2582 
2583 #define FLEXRAY_CCSR_MTD_MASK                    (0x1000U)
2584 #define FLEXRAY_CCSR_MTD_SHIFT                   (12U)
2585 #define FLEXRAY_CCSR_MTD_WIDTH                   (1U)
2586 #define FLEXRAY_CCSR_MTD(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCSR_MTD_SHIFT)) & FLEXRAY_CCSR_MTD_MASK)
2587 /*! @} */
2588 
2589 /*! @name CCFR - MB Cycle Counter Filter */
2590 /*! @{ */
2591 
2592 #define FLEXRAY_CCFR_CCFVAL_MASK                 (0x3FU)
2593 #define FLEXRAY_CCFR_CCFVAL_SHIFT                (0U)
2594 #define FLEXRAY_CCFR_CCFVAL_WIDTH                (6U)
2595 #define FLEXRAY_CCFR_CCFVAL(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_CCFVAL_SHIFT)) & FLEXRAY_CCFR_CCFVAL_MASK)
2596 
2597 #define FLEXRAY_CCFR_CCFMSK_MASK                 (0xFC0U)
2598 #define FLEXRAY_CCFR_CCFMSK_SHIFT                (6U)
2599 #define FLEXRAY_CCFR_CCFMSK_WIDTH                (6U)
2600 #define FLEXRAY_CCFR_CCFMSK(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_CCFMSK_SHIFT)) & FLEXRAY_CCFR_CCFMSK_MASK)
2601 
2602 #define FLEXRAY_CCFR_CCFE_MASK                   (0x1000U)
2603 #define FLEXRAY_CCFR_CCFE_SHIFT                  (12U)
2604 #define FLEXRAY_CCFR_CCFE_WIDTH                  (1U)
2605 #define FLEXRAY_CCFR_CCFE(x)                     (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_CCFE_SHIFT)) & FLEXRAY_CCFR_CCFE_MASK)
2606 
2607 #define FLEXRAY_CCFR_CHB_MASK                    (0x2000U)
2608 #define FLEXRAY_CCFR_CHB_SHIFT                   (13U)
2609 #define FLEXRAY_CCFR_CHB_WIDTH                   (1U)
2610 #define FLEXRAY_CCFR_CHB(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_CHB_SHIFT)) & FLEXRAY_CCFR_CHB_MASK)
2611 
2612 #define FLEXRAY_CCFR_CHA_MASK                    (0x4000U)
2613 #define FLEXRAY_CCFR_CHA_SHIFT                   (14U)
2614 #define FLEXRAY_CCFR_CHA_WIDTH                   (1U)
2615 #define FLEXRAY_CCFR_CHA(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_CHA_SHIFT)) & FLEXRAY_CCFR_CHA_MASK)
2616 
2617 #define FLEXRAY_CCFR_MTM_MASK                    (0x8000U)
2618 #define FLEXRAY_CCFR_MTM_SHIFT                   (15U)
2619 #define FLEXRAY_CCFR_MTM_WIDTH                   (1U)
2620 #define FLEXRAY_CCFR_MTM(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_CCFR_MTM_SHIFT)) & FLEXRAY_CCFR_MTM_MASK)
2621 /*! @} */
2622 
2623 /*! @name FIDR - MB FID */
2624 /*! @{ */
2625 
2626 #define FLEXRAY_FIDR_FID_MASK                    (0x7FFU)
2627 #define FLEXRAY_FIDR_FID_SHIFT                   (0U)
2628 #define FLEXRAY_FIDR_FID_WIDTH                   (11U)
2629 #define FLEXRAY_FIDR_FID(x)                      (((uint16_t)(((uint16_t)(x)) << FLEXRAY_FIDR_FID_SHIFT)) & FLEXRAY_FIDR_FID_MASK)
2630 /*! @} */
2631 
2632 /*! @name IDXR - MB Index */
2633 /*! @{ */
2634 
2635 #define FLEXRAY_IDXR_MBIDX_MASK                  (0x1FFU)
2636 #define FLEXRAY_IDXR_MBIDX_SHIFT                 (0U)
2637 #define FLEXRAY_IDXR_MBIDX_WIDTH                 (9U)
2638 #define FLEXRAY_IDXR_MBIDX(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_IDXR_MBIDX_SHIFT)) & FLEXRAY_IDXR_MBIDX_MASK)
2639 /*! @} */
2640 
2641 /*! @name MBDOR - MB Data Field Offset */
2642 /*! @{ */
2643 
2644 #define FLEXRAY_MBDOR_MBDO_MASK                  (0xFFFFU)
2645 #define FLEXRAY_MBDOR_MBDO_SHIFT                 (0U)
2646 #define FLEXRAY_MBDOR_MBDO_WIDTH                 (16U)
2647 #define FLEXRAY_MBDOR_MBDO(x)                    (((uint16_t)(((uint16_t)(x)) << FLEXRAY_MBDOR_MBDO_SHIFT)) & FLEXRAY_MBDOR_MBDO_MASK)
2648 /*! @} */
2649 
2650 /*! @name LEETR - LRAM ECC Error Test Register */
2651 /*! @{ */
2652 
2653 #define FLEXRAY_LEETR_LEETD_MASK                 (0xFFFFU)
2654 #define FLEXRAY_LEETR_LEETD_SHIFT                (0U)
2655 #define FLEXRAY_LEETR_LEETD_WIDTH                (16U)
2656 #define FLEXRAY_LEETR_LEETD(x)                   (((uint16_t)(((uint16_t)(x)) << FLEXRAY_LEETR_LEETD_SHIFT)) & FLEXRAY_LEETR_LEETD_MASK)
2657 /*! @} */
2658 
2659 /*!
2660  * @}
2661  */ /* end of group FLEXRAY_Register_Masks */
2662 
2663 /*!
2664  * @}
2665  */ /* end of group FLEXRAY_Peripheral_Access_Layer */
2666 
2667 #endif  /* #if !defined(S32Z2_FLEXRAY_H_) */
2668